Section 5: Computer Organisation and Architecture Flashcards
Chapter 25:
What are the three main busses in a computer?
Control Bus.
Data Bus.
Address Bus.
Chapter 25:
What are the six main components of the CPU?
Control Unit. (CU) Arithmetic Logic Unit. (ALU) Registers. Cache. Busses. Clock.
Chapter 25:
What does the Control Unit do?
Coordinates and Controls all operations carried out by the computer.
Follows the Fetch-Decode-Execute Cycle.
Chapter 25:
What does each stage of the Fetch-Decode-Execute Cycle do?
Fetch:
Causes the next instruction to be fetched from main memory.
Decode:
Decodes the instruction.
Execute:
Runs the instruction.
Chapter 25:
What are the two types of operation that the ALU can perform?
Arithmetic.
Logical.
Chapter 25:
What are Arithmetic operations in the ALU?
Deal with values.
Add.
Subtract.
Multiply.
Divide.
Chapter 25:
What are Logical operations in the ALU?
Deal with comparisons and switches.
NOT. AND. OR. XOR. NAND. NOR. XNOR. Buffer. & Shifts.
Chapter 25:
What are Registers?
Memory cells that operate at very high speeds, due to the small distance to travel; being inside the CPU.
Chapter 25:
What is a bus (in a computer)?
A set of parallel wires (“lines”) connecting two or more components of a computer.
Speed measured in Megahertz (MHz).
Chapter 25:
What do the Address Bus, Data Bus, and Control Bus do?
When the CPU wants to access a particular memory location, a signal is sent down the Address Bus to the main memory.
The data will then be transferred either from Memory to the CPU, or from the CPU to Memory. The data is transferred across the Data Bus.
The Control Bus carries commands to, and status reports from other hardware devices. The Control Bus also carries Clock Pulses, which help to keep the system under control and stop conflicts (queue transfers).
Chapter 25:
What is the “size” or “width” of a bus?
How many bits can be transferred at once. (How many lines it has)
64-bit computers have 64-bit bus widths.
Chapter 25:
A Bus is a collection of wires. What are these wires called?
Lines.
Chapter 25:
Are the following busses Unidirectional or Bidirectional?
Address Bus, Data Bus, Control Bus
Address Bus = Unidirectional.
Data Bus = Bidirectional.
Control Bus = Bidirectional.
Chapter 25:
What are Address Busses, Data Busses, and Control Busses known collectively as?
The System Bus.
Chapter 25:
What is a transmission medium?
Give an example of a transmission medium in a computer?
Where something can mediate the propagation of signals. (Sync signals to avoid collisions).
Busses are an example.
Chapter 25:
Control Busses have 7 Control Signals. List them.
Memory Write: causes data on the data bus to be written to a specified location.
Memory Read: causes data from a specified location to be placed into the data bus.
Interrupt Request: indicates that a device is requesting access to the CPU.
Bus Request: indicates that a device is requesting access to the Data Bus.
Bus Grant: indicates that the CPU has granted access to the Data Bus.
Clock Pulse: used to synchronise operations.
Reset: initialises all components.
M(WR) I B(RG) C R
Chapter 25:
How does the width of the Data Bus effect the overall system performance?
Data Bus is typically made of 8, 16, 32, or 64 lines.
When a 64-bit instruction needs to be sent down a 32-bit Data Bus, the instruction needs two calls to be sent.
This involves splitting the instruction up, as well as sending double the transmissions.
Chapter 25:
Memory is divided up internally into units.
What are these units called?
Typically how large are they?
Words.
Typically 8, 16, 32, or 64 bits in size.
Different CPUs use different sizes.
Chapter 25:
Which System Bus determines the maximum possible memory capacity of a computer system?
Why?
The Address Bus.
The Address Bus cannot map one combination of its bits to more than one memory location.
Chapter 25:
What is the maximum theoretical memory capacity of a 64-bit PC?
16,777,216 TiB (Tebibytes)
2^64 (B) /1024 (KiB) /1024 (MiB) /1024 (GiB) /1024 (TiB)
Chapter 25:
What is the maximum theoretical memory capacity of a 32-bit PC?
4 GiB (Gibibytes)
2^32 (B)
/1024 (KiB)
/1024 (MiB)
/1024 (GiB)
Chapter 25:
What is an I/O controller?
A device that interfaces between an input or output device, and the CPU.
I/O controllers are unique to the input/output device.
Chapter 25:
How does an I/O controller connect to the CPU?
Via the control bus.
Chapter 25:
How are instructions send from the CPU, through the I/O controller, into the device?
CPU sends and input/output request to the I/O controller.
The I/O controller receives this, and sends device-specific control signals to the device. It also manages the data flow to and from the device.
Chapter 25:
What are the three main parts to an I/O controller?
An interface that connects the controller to the device system.
A set of data, command, and status registers.
An interface that connects the controller to the computer’s CPU.
Chapter 25:
What is an interface?
A standardised form of connection defining such things as signals, number of connecting pins/sockets, and voltage levels
Chapter 25:
What is an example of an interface?
Universal Serial Bus (USB)
Chapter 25:
What is the stored program concept?
Machine Code instructions are fetched and executed serially by a processor that performs arithmetic and logical operations.
Chapter 25:
What makes Von Neumann’s design special?
Data and Instructions are stored as binary in the same memory.
Chapter 25:
Other than Von Neumann Architecture, what is the other common CPU Architecture used?
Harvard Architecture.
Chapter 25:
What is the main difference between Von Neumann Architecture and Harvard Architecture?
In Von Neumann Architecture, Data and Instructions are stored in the same memory.
In Harvard Architecture, Data and Instructions are stored in different memories.
Chapter 25:
What is DSP?
Digital Signal Processing.
Take a Digital Signal, Process (adapt) it into a different one.
Often used to improve the sound quality of an audio file.
Chapter 25:
What are advantages to Harvard Architecture?
Where is it used?
Can be faster, as Data and Instructions can be fetched in parallel, rather than competing for the same bus.
Used often in Digital Sound Processing (DSP).
Chapter 25:
What are disadvantages to Harvard Architecture?
Having multiple data busses and memories comes with cost.
Increased Hardware complexity.
Can execute some instructions slower.
Chapter 25:
What direction are the connections between the Address Bus and the following components?
Processor, Main Memory, Keyboard Input Controller, VDU Output Controller, Disk I/O Controller.
AB from Processor, AB to Main Memory, AB to Keyboard Input Controller, AB to VDU Output Controller, AB to Disk I/O Controller.
Chapter 25:
What direction are the connections between the Data Bus and the following components?
Processor, Main Memory, Keyboard Input Controller, VDU Output Controller, Disk I/O Controller.
Data Bus to&from Processor, Data Bus to&from Main Memory, Data Bus from Keyboard Input Controller, Data Bus to VDU Output Controller, Data Bus to&from Disk I/O Controller.
Chapter 25:
What direction are the connections between the Control Bus and the following components?
Processor, Main Memory, Keyboard Input Controller, VDU Output Controller, Disk I/O Controller.
Data Bus to&from Processor,
Data Bus to&from Main Memory,
Data Bus to&from Keyboard Input Controller,
Data Bus to&from VDU Output Controller,
Data Bus to&from Disk I/O Controller.
Chapter 26:
What are the components of the CPU?
Control Unit (CU) Arithmetic Logic Unit (ALU) The System Clock General-purpose registers Dedicated registers
Cache
Busses
Chapter 26:
What does the Control Unit do?
Controls and coordinates the activities of the CPU, directing the flow of data between the CPU and other devices.
Accepts the next instruction, breaks it down, into sequential steps, manages the execution, and stores the resulting data back into memory or registers.
Chapter 26:
What does the System Clock do?
Generates a pulse, switching between 0 and 1 billions of times per second.
All CPU operations are synced to these pulses.
Chapter 26:
What is a System Clock pulse?
Where the clock value changes from 0 to 1, or 1 to 0 (depending on the CPU) .
This happens billions of times per second.
3 GHz clock = 3 Billion pulses per second.
Chapter 26:
What is a general-purpose register?
Small storage located inside the CPU.
They store the results of arithmetic and logical operations from the ALU.
There are typically 16 registers in a CPU ( R0, R15 ).
Chapter 26:
What format does the CPU follow to execute instructions?
The Fetch-Decode-Execute Cycle.
Also known as the Fetch-Execute Cycle.
Chapter 26:
What are the 6 main Dedicated Registers?
Also known as Special-purpose Registers:
Program Counter. (PC)
Current Instruction Register. (CIR)
Memory Address Register. (MAR)
Memory Buffer/Data Register. (MBR)/(MDR)
Status Register. (SR)
Accumulator. (ACC) (Often considered general-purpose)
Chapter 26:
What happens during the Fetch stage of the Fetch-Decode-Execute Cycle?
- The Address of the next instruction, stored in the Program Counter, is copied over to the Memory Address Register. From here, the Address is sent down the Address Bus to main memory.
- The instruction held at that Address is returned along the data bus to the Memory Buffer/Data Register.
The content of the Program Counter is also incremented to prepare for the next instruction. - Content of the Memory Buffer/Data Register is copied over to the Current Instruction Register.
Chapter 26:
What happens during the Decode stage of the Fetch-Decode-Execute Cycle?
- The instruction in the Current Instruction Register is sent to the Decode Unit, where it is split into opcode and operand, and returned to the CIR.
Additional Data is Fetched if required.
Chapter 26:
What happens during the Execute stage of the Fetch-Decode-Execute Cycle?
- The instruction is Executed, using the ALU if required.
Results are stored in the Accumulator, general-purpose registers, or main memory.
Chapter 26:
When is the Program Counter NOT incremented by 1 in the Fetch stage?
When there is a Jump, or Branch call.
Chapter 26:
What factors affect the processor performance in a computer?
The number of cores.
Clock speed.
Amount, and type of cache memory.
Word length.
Address Bus width.
Data Bus Width
