Section 3: Software Synchronization Flashcards
Define CPU latency
Time between the receipt of a service request and the initiation of the service. Can involve both hardware and software delays.
Define real-time system
A system that guarantees a worst-case latency for critical events
Define latency
The delay between the arrival of the request and the completion of service.
What are two terms that are used in discussing system performance?
Latency and Throughput
Define throughput
A measure of how many items can be processed per unit of time.
Define blind cycle
Software waits for some amount of time Ned then acts on the data whether or not the device is ready
Define periodic polling
Device status is checked after a pre-determined amount of time and this repeats until the device is done. Usually implemented with a timer interrupt.
Define occasional polling
Device status is checked at the convenience of the designer
Define tight polling loop (gadfly or busy waiting)
Software continually checks the I/O status, waiting for the device to be done.
Define interrupt handling
Device generates a hardware interrupt to request servicing when done.
Name 5 synchronization mechanisms
- Blind cycle
- Periodic polling
- Occasional polling
- Tight polling
- Interrupt handling.
Which 3 synchronization mechanisms are CPU-orientated?
- Blind cycle
- Periodic polling
- Occasional polling
Synchronization is dependant primarily on CPU timing.
List 2 synchronization mechanics that are device-orientated
- Tight polling
- Interrupt handling
Latency seen by the device is minimized.
Explain the steps in input polling loop synchronization
- Poll the device
- Wait until data is available
- Input the data
Explain the steps in output polling loop synchronization
- Poll the device
- Wait until device is ready
- Output data
Explain the steps in interrupt synchronization
- A device notifies CPU of interrupt request
- CPU completes execution of the current instruction
- Execution of main program is suspended
- Interrupts are disabled
- Some internal registers are saved (including program counter)
- Device may be acknowledged
- Interrupt service routine is selected
- Interrupt service routine is executed
- Registers are restored
- Interrupts are enabled
- Execution of main program resumes
Why should interrupt service routines (ISR) execute as fast as possible?
Because they are interrupting other tasks
Explain the structure of an interrupt service routine (ISR)
- Save any registers modified by the ISR
- Acknowledge the device
- Re-enable interrupts to allow higher or same priority interrupts (design specific)
- Test for a valid interrupt and / or determine the exact source of the interrupt
- Complete desired action
- Restore registers
- Return from interrupt
What is the difference between vectored and non-vectored interrupts?
Vectored interrupts have a fixed priority associated with the interrupt vector. In non-vectored interrupts, the software must determine priority and which ISR goes with each interrupt.
Explain the steps in interrupt initialization
- Disable all interrupts
- Enable device interface interrupts by setting appropriate device interface registers
- Set interrupt mask to allow interrupt from device
- Initialize interrupt vector with address of ISR
- Enable interrupts as required
