Sec 5. Chap 26 : The Processor. Flashcards
ALU.
Arithmetic Logic Unit
Mathematical operations.
Completes add / subtract / multiply / shift operations / bool logic on floating point values
Control Unit
Directs the operation of the processor. It tells the computer’s memory, arithmetic and logic unit and input and output devices how to respond to the instructions that have been sent to the processor.
System clock.
Generates pulses, a series of signals between 0 and 1 billions of time a second - regulates the timing and flow of all computer functions
General purpose registers
Stores temporary data within the microprocessor.
Accumulator
the accumulator is a register in which intermediate arithmetic and logic results are stored.
Program counter (PC)
Holds the address of the next instruction to be executed
Current instruction register (CIR)
holds the current instructions being executed (CIR)
Memory address register (MAR)
In a computer, the memory address register is the CPU register that either stores the memory address from which data will be fetched to the CPU, or the address to which data will be sent and stored. In other words, MAR holds the memory location of data that needs to be accessed.
Memory buffer register (MBR)
Stores information that is being sent to, or received from, the memory along the bidirectional data bus.
Status register (SR)
A collection of status flag bits, such as interrupt enabled bits, that changes depending on the previous outcome of an execution.
Fetch execute cycle
Fetch stage
- Address of the next instruction coped from the Programme counter to the memory address register.
- This instruction is sent to the Memory buffer register along the data bus. Programme counter is incremented for the next address.
- Contents of the Memory Buffer Register are coped to the Current Instruction Register.
Fetch execute cycle
Decode stage
- Instruction held in the Current instruction register is decoded. Instruction split into opcode and operand.
(OP code determines instruction type and what hardware to use)
Fetch execute cycle
Execution stage
- Instruction is executed using the Arithmetic logic Unit. Results stored in the general purpose registers / memory.
Factors affecting processor performance
list
Core count amount / speed of cache clock speed word length address / data bus width
Cache
Small amount of memory next to the cpu - instructions are fetched from ram and are copied to the cache so that if they are needed again it does not need to be sent for again. Reduces average cost to access data from main memory.
Interrupts
Interrupts are signals sent to the CPU by external devices, normally I/O devices. They tell the CPU to stop its current activities and execute a new process.
Interrupt service routine.
An interrupt service routine (ISR) is a software routine that hardware invokes in response to an interrupt. ISR examines an interrupt and determines how to handle it executes the handling. Once completed the original values are loaded of the stack (process resumes).
Interrupt check after each cycle.
Start -> execute cycle -> interrupt?
if interrupt = true
status register set and
ISR called.
-> start
if interrupt = false
start
Processor instruction set.
Machine code instructions have two sections for each word.
Operation code (opcode) is made up of the basic machine operation and the addressing mode.
How the operand is used is determined by the addressing mode.
Addressing mode.
Immediate addressing : Operand is the actual call to be operated on.
Direct addressing : Operand holds the memory address of the value to be operated on.
