Processors

Question 1

RISC and its properties

Answer 1

Reduced Instruction Set Computer
Has a **small **instruction set
Each instruction ~ one line of machine code, takes one clock cycle.
Allows for pipelining, requires more RAM, computer has to work more to translate high level code into machine code.

Question 2

CISC and its properties

Answer 2

Complex instruction Set Computer
Large instruction set
Aims to complete tasks in as few lines of assembly code as possible.
Used in embedded systems and microcontrollers. Old fashioned, replaced by RISC.
Requires less RAM, compiler works less to translate high level to machine, many specialised instructions are made. (i.e MULT A,B)

Question 3

Concurrent processing

Answer 3

Two or more actions in process at the same time.

Question 4

Parallel processing

Answer 4

Two or more actions executing simultaneously.

Question 5

Contemporary processing

Answer 5

Uses a mixture of Von Neumann and Harvard Architecture.

Von Neumann used for working with data and instructions in main memory. Harvard used to divide cache into instruction and data cache.

Question 6

Parallel system

Answer 6

Multiple instructions can be completed in any given time. Doesn’t need multiple cores, uses threading and pipelining.

Question 7

Multicore system

Answer 7

A processor with **multiple processing units. **
Each processing unit can complete FDE cycles independently, so multiple instructions processed simultaneously.
Usually perform better in large projects.
Consumes less power, support higher clock rates, more efficient than multiple single core processors.

Question 8

GPU

Answer 8

A coprocessor made up of independent parallel processors. Effective at completing repetitive tasks.

Question 9

Uses of GPU’s

Answer 9

Image processing and Machine learning.

Question 10

Fetch stage of FDE Cycle

Answer 10

-Address from PC is copied to MAR
- Instruction held at address is copied to MDR by data bus, PC increments by 1
- Value of MDR is copied to CIR

Question 11

Decode Stage of FDE cycle

Answer 11

CIR’s contents split into opcode and operand.

Question 12

Execute stage of FDE cycle

Answer 12

Opcode is executed on the data

Question 13

Registers

Answer 13

High speed memory locations that store data/instructions.

Question 14

Von Neumann Architecture

Answer 14

Instructions and data stored in shared memory and shared data bus
5 registers
one ALU
one control unit

Question 15

Harvard Architecture

Answer 15

Instructions and data stored in separate memory and data buses.

Question 16

Opcode

Answer 16

Used to determine the type of instruction and what hardware to use to execute it.

Question 17

Operand

Answer 17

Holds the address of where the operation is performed.

Question 18

Bus

Answer 18

A collection of parallel wires combining >=2 components together

Question 19

Data bus

Answer 19

Bidirectional bus that transports data and instructions between components.

Question 20

Address bus

Answer 20

Used to transmit memory address specifying where data is to be sent or retreived from.

Question 21

Control bus

Answer 21

bidirectional bus used to transmit control signals between internal and external components.

Question 22

Bus request and grant

Answer 22

Bus request- device is requesting access to data bus
Bus grant- CPU grants access to data bus

Question 23

Memory write

Answer 23

Causes data to be written into addressed location

Question 24

Memory read

Answer 24

causes data from addressed location to be placed onto address bus.

Question 25

Interrupt request control signal

Answer 25

Indicates device is requesting access to CPU.

Question 26

Clock signal

Answer 26

Used to synchronise instructions.

Question 27

MAR

Answer 27

Holds address of location that is to be read from/written to.

Question 28

MDR

Answer 28

Temporarily stores data that has just been read from/ that needs to be written.

Question 29

CIR

Answer 29

Holds current instruction divided into opcode and operand.

Question 30

Accumulator

Answer 30

Stores results from arithmetic/logical operations, acts as buffer in I/O processors.

Question 31

PC

Answer 31

Holds address of next instruction to be executed. Increments by 1 to point to next instruction. If instruction is to jump, its contents are copied to MAR, and PC increments to address of the instruction being jumped to.

Question 32

Control Unit

Answer 32

Part of processor which directs operations in the CPU