Processors Flashcards
RISC and its properties
Reduced Instruction Set Computer
Has a **small **instruction set
Each instruction ~ one line of machine code, takes one clock cycle.
Allows for pipelining, requires more RAM, computer has to work more to translate high level code into machine code.
CISC and its properties
Complex instruction Set Computer
Large instruction set
Aims to complete tasks in as few lines of assembly code as possible.
Used in embedded systems and microcontrollers. Old fashioned, replaced by RISC.
Requires less RAM, compiler works less to translate high level to machine, many specialised instructions are made. (i.e MULT A,B)
Concurrent processing
Two or more actions in process at the same time.
Parallel processing
Two or more actions executing simultaneously.
Contemporary processing
Uses a mixture of Von Neumann and Harvard Architecture.
Von Neumann used for working with data and instructions in main memory. Harvard used to divide cache into instruction and data cache.
Parallel system
Multiple instructions can be completed in any given time. Doesn’t need multiple cores, uses threading and pipelining.
Multicore system
A processor with **multiple processing units. **
Each processing unit can complete FDE cycles independently, so multiple instructions processed simultaneously.
Usually perform better in large projects.
Consumes less power, support higher clock rates, more efficient than multiple single core processors.
GPU
A coprocessor made up of independent parallel processors. Effective at completing repetitive tasks.
Uses of GPU’s
Image processing and Machine learning.
Fetch stage of FDE Cycle
-Address from PC is copied to MAR
- Instruction held at address is copied to MDR by data bus, PC increments by 1
- Value of MDR is copied to CIR
Decode Stage of FDE cycle
CIR’s contents split into opcode and operand.
Execute stage of FDE cycle
Opcode is executed on the data
Registers
High speed memory locations that store data/instructions.
Von Neumann Architecture
Instructions and data stored in shared memory and shared data bus
5 registers
one ALU
one control unit
Harvard Architecture
Instructions and data stored in separate memory and data buses.
Opcode
Used to determine the type of instruction and what hardware to use to execute it.
Operand
Holds the address of where the operation is performed.
Bus
A collection of parallel wires combining >=2 components together
Data bus
Bidirectional bus that transports data and instructions between components.
Address bus
Used to transmit memory address specifying where data is to be sent or retreived from.
Control bus
bidirectional bus used to transmit control signals between internal and external components.
Bus request and grant
Bus request- device is requesting access to data bus
Bus grant- CPU grants access to data bus
Memory write
Causes data to be written into addressed location
Memory read
causes data from addressed location to be placed onto address bus.
Interrupt request control signal
Indicates device is requesting access to CPU.
Clock signal
Used to synchronise instructions.
MAR
Holds address of location that is to be read from/written to.
MDR
Temporarily stores data that has just been read from/ that needs to be written.
CIR
Holds current instruction divided into opcode and operand.
Accumulator
Stores results from arithmetic/logical operations, acts as buffer in I/O processors.
PC
Holds address of next instruction to be executed. Increments by 1 to point to next instruction. If instruction is to jump, its contents are copied to MAR, and PC increments to address of the instruction being jumped to.
Control Unit
Part of processor which directs operations in the CPU
