Processor Performance Flashcards

1
Q

What does the width of the address bus determine?

A
  • Width of the address bus determines the maximum possible memory addresses/memory capacity of the system.
  • Maximum size of RAM.
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2
Q

What does it mean for the data bus to be bi-directional?

A

Data can be sent both ways along the bus.

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3
Q

What is the width of the data bus defined by?

A

Width of the data bus is defined by the number of wires or lines it contains.

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4
Q

What does the data bus do?

A

Data bus transmits the data held in a word of memory, between processor components and memory.

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5
Q

How does the width affect the data bus?

A

• The size of the data bus determines the maximum size of an operand in an instruction.

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6
Q

What does the maximum size of the operand depend on?

A

The maximum size of the operand depends on the width of the address bus.

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7
Q

What are the main factors affecting processor performance?

A
  • Clock speed
  • Number of cores in the processor
  • Amount and type of cache memory.
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8
Q

How does the clock speed affect performance?

A
  • The fetch execute cycle is triggered by the clock pulses of the system clock
  • Faster the clock speed, the faster a computer can fetch, decode and execute instructions.
  • CPU cannot perform operations faster than the clock cycle.
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9
Q

What does the system clock do?

A

Generates a series of signals, switching between 0 and 1, and synchronising CPU operations.

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10
Q

how do CPU operations relate to the system clock?

A
  • Each CPU operation starts as the clock changes from 0 to 1.
  • The CPU cannot perform operations faster than the clock cycle.
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11
Q

How does number of cores affect processor speed?

A

Each core is able to process a different instruction at the same time, with its own fetch execute cycle, meaning an increase in cores can increase the number of cycles concurrently happening, increasing performance.

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12
Q

What is parallel processing/

A

Using several processor cores working at the same time.

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13
Q

How does parallel processing affect the fetch execute decode cycle?

A

• Each core can concurrently work on different parts of the same task

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14
Q

What is a drawback to parallel processing?

A

Instructions are processed sequentially, parallel processing is therefore not always possible.

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15
Q

What is cache?

A

A small amount of super fast memory that stores data and instructions that have been recently used by the processor.

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16
Q

What is cache split into, and how is this advantageous?

A
  • Cache memory is split into instruction and data cache.

* This allows data and instructions to be fetched simultaneously.

17
Q

How does cache memory affect performance?

A

• The more cache memory a computer has, the more likely it is that it will not have to fetch the next instruction or data from RAM, as it will already have been loaded into the super fast cache memory from which it can be retrieved much more quickly.

18
Q

What is pipe-lining?

A

Overlapping stages in the fetch execute cycle, or breaking down the stages in an arithmetic instruction, this is designed to improve performance.

19
Q

What are the different levels of cache?

A
  • Level 1 cache, extremely fast but small.
  • Level 2 cache, fairly fast but medium sized.
  • Level 3 cache