Pipelines Flashcards
What is the purpose of status flags?
Programs may need to execute some parts conditionally.
Done by conditionally branching to another part of code.
It decides when to branch via the use of status flags, stored in the status register.
Four most common status flags (CPSR)
N: Last operation yielded negative result (bit 7 of the ALU result)
Z: Last operation yielded 0 result (NOR all bits of the ALU together)
V: Overflow bit (carryout value)
C: Carry flag
How to generate status flags
Easy to generate the signal.
Then we just need a bit of logic to update the status register in the right state depending on which instruction has been executed.
Explain the bit format of branch instructions
All branch instructions are in the form xxy10000
The xx bits encode which status flag the branch is based on (use multiplexors to select the correct flag)
The status flag is then compared with the value in y
If they are equal the branch is taken
Otherwise it isn’t.
Explain the fetch stage of the CPU cycle
The opcode of the instruction is fetched from memory.
CPU puts the address in the program counter onto the address bus
Memory system places the required data value onto the data bus.
CPU reads the value from the data bus into a temporary “register” called the instruction register.
Explain the decode stage of the CPU cycle
Opcode is decoded to decide what parts of the CPU are needed
Explain the execute stage of the CPU cycle
CPU processes / executes the instruction.
Might need to access memory again.
Then repeat for the next instruction.
How many clock cycles will it take to complete one fetch-decode-execute cycle
At minimum 3 clock cycles (1 cycle for each stage).
Explain instruction pipelining
Instruction pipelining is a technique used in CPUs to improve performance by overlapping the execution of multiple instructions, dividing the process into stages (e.g., fetch, decode, execute). Each stage works concurrently on different instructions, allowing the CPU to complete one instruction per cycle after the pipeline is filled, increasing throughput.
Pipeline Hazards
Explain structural hazards
Structural hazards occur when the design of a CPU doesn’t allow two operations to happen in parallel.
For example, in instruction pipelining, multiple stages may require you to fetch data, but it might not be possible to fetch multiple values in the same time.
What’s the solution to structual hazards?
Delay one of the stages until the next clock cycle (or however many clock cycles until there would be no clash).
This is called a bubble.
Define pipeline bubbles
A pipeline bubble is a delay in an instruction pipeline caused by a stall, where one or more stages remain idle.
Pipeline hazards introduce bubbles into the pipeline.
Pipeline Hazards
Explain control hazards
Branches can cause control hazards.
Happens when the proper instruction can’t be executed because a different instruction was fetched and decoded.
With a conditional branch, cannot know which instruction to execute next until branch condition is evaluated.
What’s the solution to control hazards?
Discard the currently fetch and decoded instruction and start again for the correct one.
Causes a stall one cycle less than the length of the pipeline.
Branch Prediction
Instead of always fetching the next instruction in memory, CPU uses the past to predict how a branch will be taken.
Define speculative execution
Speculative execution is a performance optimization technique where a processor predicts the outcome of instructions or branches and executes them ahead of time. If the prediction is correct, the results are used, reducing idle time. If incorrect, the speculative results are discarded.
Advantage of longer pipeline length
Smaller steps do less and take less time to run, thus CPU’s can run at a higher clock speed.
Disadvantage of longer pipeline length
More stages means the cost of a stall becomes much greater, as you have to re-process a lot more stages.
