PCIe Flashcards
When was PCIe bus introduced and by who?
2004, Intel
What application PCIe was originally targetting?
Audio and video streaming
What was the clock speed of PCI?
33 MHz
How many bits in PCIe data bus? What is the bandwidth of PCI bus?
32 bits, 132 MB/s
What bus topology does PCI use?
Shared
Difference between PCI vs. PCIe…
Shared bus for PCI; point-to-point for PCIe
The most notable PCI Express advancement over PCI is its point-to-point bus topology. The shared bus used for PCI is replaced with a shared switch, which gives each device its own direct access to the bus. Unlike PCI, which divides bandwidth between all devices on the bus, PCI Express provides each device with its own dedicated data pipeline. Data is sent serially in packets through pairs of transmit and receive signals called lanes, which enable 250 MB/s bandwidth per direction, per lane. Multiple lanes can be grouped together into x1 (“by one”), x2, x4, x8, x12, and x16 lane widths to increase bandwidth to the slot and achieve up to 4 GB/s total throughput.
What is the primary difference between PCI bus and PCIe bus?
Unlike PCI, which divides bandwidth between all devices on the bus, PCI Express provides each device with its own dedicated data pipeline.
Compatibility of PCI and PCIe
- Up-plugging is available; down-plugging isn’t
- Software compatibility exists through PCI standard, which saves user and vendor investments
Choosing the Right PC to Host PCI Express Boards
Today, most PCs are shipped with a combination of PCI and PCI Express slots. The most common PCI Express slot sizes are x1 and x16. The x1 slots are typically general-purpose and the x16 slots are used for graphics cards or other high-performance devices. Generally, x4 and x8 slots are used only in server-class machines.
What is a server-class machine?
the definition of a server-class machine is one with at least 2 CPUs and at least 2GB of physical memory.
Routing consideration for high-speed signals
does not recommend high-speed signal references to power planes. Routing across a plane split or a void in the reference plane forces return high-frequency current to flow around the split or void, which may result in the following conditions:
1. Excessradiatedemissionsfromanunbalancedcurrentflow
2. Delaysinsignalpropagationdelaysduetoincreasedseriesinductance
3. Interferencewithadjacentsignals
4. Degradedsignalintegrity(thatis,morejitterandreducedsignalamplitude)
In keeping with the above recommendations, the K2G GP EVM routes the PCIe si
What does PCIe stand for?
Peripheral Component Interconnect Express
What is NVMe?
Non-Volatile Memory (Express) or NVMe is a communication transfer protocol (or language) developed specially for SSDs
Existing HDD/SDD vs. NVMe command queue…
HDDs and SSDs have only one command queue and can send 32 commands per queue. NVMe has 64,000 command queues and can send 64,000 commands per queue.
