Part 1

Question 1

Why does it matter how many bits you use for a given data type?

Answer 1

arithmetic operations on larger bits of data (i.e. 32 bit) generate more heat than say 8 bit data

Question 2

How many numbers can be stored in an unsigned 8 bit representation AND from which number until which one.

Answer 2

256. From 0 to 255

Question 3

What is wrong with sign-magnitude representation?

Answer 3

It wastes one number in 0 and -0 and allows only a range from -127 unitl 127. Only 255 numbers

Question 4

How does 2s complement representation work?

Answer 4

It’s an alternative to sign-magnitude and it works by changing the value of the MBS from positive to negative

Question 5

What are the benefits of 2s complement?

Answer 5

It allows a range of 256 numbers and the circuitry for addition is the same as for subtraction- -128 to 127

Question 6

What is a disadvantage of 2s complement

Answer 6

When you are subtracting a smaller number from a larger number you get a lot of negative numbers which translates into a lot of bit flips generating a lot of heat

Question 7

What’s wrong with floating point numbers?

Answer 7

Precision: Dividing a very large number by a very small one might result in an inaccurate output

Question 8

What is the definition of a proposition?

Answer 8

We can tell whether statement is true or false and it’s unambiguous. “It is true that”

Question 9

What is the complement of: e = x or y or z

Answer 9

(not)e = (not)x and (not)y and (not)z

Question 10

Minterms and maxterms. Where do they appear? and what are they equivalent to?

Answer 10

Minterms are products and appear in DNF. Maxterms are sums and appear in CNF

Question 11

What is the difference between a PMOS and a NMOS transistor?

Answer 11

PMOS is initially closed and allows current to flow. It opens when applied 1. NMOS is initially open and closes when applied a 1

Question 12

In an inverter, which transistor is open and which is closed when A is set to VDD

Answer 12

NMOS (0) transistor is closed setting Q to VSS and PMOS is open (1)

Question 13

What logic gates are used for the sum and carry outputs in an adder respectively?

Answer 13

sum: xor
carry: and

Question 14

When is XOR defined to be true for multiple arguments?

Answer 14

If and only if an odd number of args is true (a XOR b XOR c)

Question 15

What is the (negative) implication of implementing a ripple-carry adder?

Answer 15

You have to wait for the signal to propagate to know the value of higher order bits

Question 16

Why do we need log2(N) number of select bits when N = number of signals to select from?

Answer 16

Because N represents the number of select signals we have and we need the appropriate number of bits to represent that amount of singals. I.e to represent 8 (select signals) we need 3 bits (which can represent up to 8 combinations)

Question 17

What is the difference between a multiplexor and a demultiplexor?

Answer 17

A multiplexor selects which input signal to propagate whereas a demultiplexor selects into which output signal to propagate the (single) input signal

Question 18

What is a ring oscillator?

Answer 18

Device composed of an odd number of inverters chained together. The output of the chain is made as an input to the start of the chain and the output oscillates between 2 voltage levels

Question 19

What does setting and resetting the latch mean in an SR latch?

Answer 19

Setting means activating S and resetting means activating R. Since the input singals are active low this means that S is activated when made 0 and R the same

Question 20

Which is the “not allowed” output in an SR latch and why is it not allowed?

Answer 20

When both inputs equal 0. It is not allowed because in this scenario both outputs would be equal to each other (1) which defeats the point of an SR latch. Q and Q’ are supposed to be inverted.

Question 21

How does a D latch work and what is its benefit over the SR latch?

Answer 21

It has 2 inputs. 1 single data input and a enable/disable (propagation) input which when set to 0 disables propagation and stores data value. The benefit it has is that it eliminates the”DE” part of the latch eliminates possibility of a “0 0” input on the SR part of the latch (which is an SR latch itself) which is the “not allowed” value

Question 22

What is “level sensitive” and “edge sensitive” and what are examples of devices that implement these concepts?

Answer 22

Level sensitiveness happens when a singal can be propagated when the clock singal is “on” or 1. An example of this are latches (i.e. D latch). Edge sensitiveness happens when a singal is propagated when the clock signal rises from 0 to 1 (but not WHILE it is 1). An example of this are flip flops (i.e. JK flip flops)

Question 23

What are timing cosntraints used for?

Answer 23

When a data singal changes, there’s a small period of time when we don’t know what is its value so timing cosntraints are used to avoid unexpected behaviour. A setup time and hold time are set to define how long before the event (clock edge) and after the event the singal should be settled

Question 24

Why does the second latch in a master slave flip flop need to have the enabler inverted?

Answer 24

The inverter prevents the data value from being propagated unless initial enabler value is 0 (which would be 1 in second D latch) enabling the data value to reach the second input and simulate only changing when falling. Basically prevents racing and replaces it with toggling

Question 25

What are the benefits of a JK flip flop?

Answer 25

If you compare it with an SR flip flop, it gets rid of the “not allowed” SR values 0 0.

Question 26

What is the problem of a simple JK flip flop and why do we need a master slave configuration?

Answer 26

The problem is that input values “1 1” lead to racing behaviour which can be eliminated by controlling it via the master slave configuration. This leads to toggling behaviour instead of an uncontrolled switching between 0 and 1 for the outputs.

Question 27

Why need for inverter for the clk value in master slave config of JK flip flop?

Answer 27

Because it makes only master OR slave operational at any given clock tick

Question 28

From a high level perspective, how do you read and write from a memory address?

Answer 28

Writing: specify that we are writing (1), set address to location, set data wires to value we want to store, hold this for the required amount of time(clock edge) so content of address changes to value of data
Reading: specify we are reading(0), set address to location, hold for required amount of time and data from location appears in data wires

Question 29

What does random access mean in RAM?

Answer 29

Each memory cell can be written or read in any order regardless of the previous cell that was accessed

Question 30

From a lower level perspective, how does reading and writing work in an SRAM cell?

Answer 30

Reading: Wordline set to 1 to allow value within the bi-stable circuit to propagate to the bitline
Writing: Set BL to nQ and BL’ to nQ’, set worldline to 1 and allow to propagate to Q and Q’ respectively

Question 31

What is the benefit of an SRAM cell vs a flip flop design?

Answer 31

You only need to use 6 transistors in the former whereas the latter requires between 12 and 30 of them

Question 32

How can you build memory from cells?

Answer 32

You connect memory locations for the same word together and connect them to a single wordline. The same word position is connected vertically via the bitline and an address decoder is used to activate a specific wordline given an address

Question 33

How can you build memory from cells?

Answer 33

You connect memory memory locations for the same word together and connect them to a single wordline. The same word position are connected vertically via the bitline and an address decoder is used to activate a specific wordline given an address

Question 34

From a lower level perspective, how does reading and writing work in a DRAM cell?

Answer 34

A DRAM cell consists of a transistor and a capacitor. The transistor allows for reading and writing (charging/discharing capacitor). However, transistor leaks current both when it’s on or off. Hence, stored value have to be refreshed periodically. This is done during write time or read time or even if these do not happen.

Question 35

How does a DRAM refresh work?

Answer 35

Use counter (in chip or peripheral logic) to hold next row to be refreshed.
Reading: entire row is read out and refresh is written back
Writing: row is read out, 1 value changes and whole row is written back

Question 36

What are the addressing width and the data width?

Answer 36

Addressing width is the number of bits holding the address locations. This number indicates the maximum addresses that is possible to store.The data width is the size of each memory location. If you multiply both you get the capacity of the chip

Question 37

How much is 1 kbit? How much is 1 KB?

Answer 37

1024 bits. 1024 * 8 bits

Question 38

What does an FSM consist of?

Answer 38

• Inputs
• Outputs
• Next state logic
• Output logic
• Internal state stored in memory

Question 39

What is the difference between a mealy and a moore machine?

Answer 39

The output of a moore machine depends solely on current state whereas the output of a mealy machine depends on inputs and current state

Question 40

How to design a FSM?

Answer 40

• Consider if it is mealy vs moore because this will impact how outputs are calculated
• Minimize number of state
• Optimize logic