Parallel architecture

Question 1

Moore’s Law

Answer 1

Empirical observation that the number of transistors on a chip doubles every 18 to 24 months

Question 2

Parallelism by Pipelining

Answer 2

Processor works on different steps of instructions at the same time.
Output of one step is input for the next
I

Question 3

What is MISD

Answer 3

Multiple Input, Single Data: There are multiple processing elements each of which has a private program memory, but there is only one common acces to a single global data memory. In each step, each processing element obtains the same data element from the data memory and loads an instruction from its private program memory.

Question 3

what is SISD

Answer 3

Single Instruction, Single Data: There is one processing element which has acces to a single program and data storage. In each step the processing element loads an instruction and the corresponding data and executes the instruction. The result is stored back in the data storage. Von Neumann architecture

Question 3

degree of parallelism

Answer 3

The number of pipeline stages

Question 4

What is SIMD

Answer 4

Single Instruction, Multiple Data: There are multiple processing elements each of which has a private acces to a (shared or distributed) data memory. In each step, each processing element obtains from the control processor and the same instruction and loads a separate data element through its private data access on which the instruction is performed

Question 4

What is MIMD

Answer 4

Multiltple Instruction, Multiple Data: There are multiple processing elements each of which has a separate instruction and data access to a (shared or distributed) program and data memory. In each step, each processing element loads a separate instruction and a separate data element, applies the instruction to the data element, and stores a possible result back into the data storage.

Question 5

CPU

Answer 5

Central Processing unit:
- Fetsch, decode, execute program instructions; fetch data, store results

Question 6

Graphics controller

Answer 6

Render display images to minotors

Question 7

GPU

Answer 7

Graphiscs Processing unit:
-perform complex graphics operations
- can also be used for other tasks

Question 8

CPU vs GPU

Answer 8

CPU:
-has several cores
GPU
-has thousands of cores
-SIMD architecture
-especially suitable for parallel proccesing

Question 9

What is DMM

Answer 9

distributed memory machines. Consist of a number of nodes. Program data are stored in local memory of one or several nodes. All local memory is private and only the local proccesor can acces the local memory directly. When a proccesor need data from the local memory of other nodes to perform local computations, message passing has to be performed via the interconnection network.

Question 10

What is a node

Answer 10

A node is an independent unit, consisting of processor and local memory

Question 11

Point-to-point connections

Answer 11

A node is connected to a fixed set of other nodes by physical connection. moslty seen in older multicomputers

Question 12

DMA controller

Answer 12

direct memory acces to the nodes to control the data transfer between local memory and the I/O controller. Has interconnection network to which nodes can issue a send operation and then continue local operations while the DMA controller executes the send operation

Question 13

What is SMM

Answer 13

Shared Memory Organization, also called globabl memory. Consists of a number of processors or cores, a shared physicall memory and an interconnection newtork to connect the processors with the memory

Question 14

What is a Cache

Answer 14

A cache is a small, but fast memory between the processor and main memory. A cache can be used to store data that is often accessed by the processor, thus avoiding expensive main memory acces. The data stored in a cache are always a subset of the data in the main memory.
several level of caches typically used, starting from small and and expensive level 1 cache (L1) over several stages (L2,L3) to the large but slow main memory.

Question 15

What is the diameter of a network

Answer 15

The maximum distance between any pair of nodes. Small diameter is desirable to ensure small distances for message tranmission

Question 16

What is the node degree of a network

Answer 16

is the maximum degree of a node of the network. The degree of a node n is the number of direct neighbor nodes of n. A small node degree is desirable to reduce the hardware overhead for the nodes

Question 17

What is bisection bandwidth of a network

Answer 17

Bisection bandwidith is the minimum number of edges that bust be removed to partition the network into two parts of equal size without any connection between the two parts. for uneven total nodes the size of the parts may differ by 1. A large bisection bandwidth is desirable to obtain large data throughputs

Question 18

What is node and edge connectivity of a network

Answer 18

The number of nodes or edges that must fail to disconnect the network. High connectivity value indicates a high reliability of the network.

Question 19

What is DRAM

Answer 19

Dynamic Random Access Memory, which the main memory is contructed by.

Question 20

what is SRAM

Answer 20

Static Random Acces Memory, which caches are made from.

Question 21

What happens during a cache hit and cache miss

Answer 21

After having received a memory acces request from the processor the cachce controller checks wether the memory adress specified belongs to the cache line which is currently sored in the cache. If this is the case a cache hit occurs, and the requested word is deliver to the processor from the cache. If cache line is note sore in cache a cache miss occurs. And the cache line is first copied from main memory into the cache before the requested word is deliver to the processor. The corresponding delay time is called “miss penalty”