Paper 1 Module 1 Flashcards
What happens at the fetch stage of the FDE cycle? (Part 1)
*The PC counter is checked as it holds the next instruction to be executed
*The contents of the PC are copied in the MAR
*The address of the next instruction is placed on the address bus
*The control unit instructs a memory read operation to allow the contents of the memory location to be transferred to the processor
What happens in the fetch stage of the FDE cycle? (Part 2, from the “CIR commands a memory read”)
*The instruction that is stored at that address is transferred using the data bus from main memory to the processor and is saved into the MBR
*PC is incremented so that it points to the next instruction
*The contents of the MDR are copied into the CIR to keep instruction safe so MDR can be used during the execute phase to store any additional data
What happens at the Decode stage of the FDE cycle?
The control unit decodes the instruction that is in the CIR. This is split into operand and opcode to determine what type of instruction needs to be carried out, checking if additional data is required from memory and figuring out where this is in memory
What happens at the execute stage of the FDE cycle?
The instruction is executed.
How does pipelining improve CPU performance?
Each task is broken down into subtasks that are handled independantly.
The next instruction can be fetched at the same time as another being decoded or executed.
The registers keep intermediate results (to not overwrite data)
Attempts to have no idle CPU time.
What is word size?
The amount of data that can be handled at one time in the processor.
Biggers word size… less data fetches to memory… more efficient processor.
What is bus width?
the number of bits that can be transferred to or from in one operation.
Charactersistics of Von neumann atchitecture.
Has a processor, ONE memory unit for data AND instructions.
Uses SAME data and address bus for transport of information between main memory and the CPU.
Advantages of Von neuman architecture.
*The control unit retrieves instruction and data in the same way from one memory unit. This simplifies the development and design of the control unit.
*The above advantage would also mean that data from memory and from devices are accessed the same way. Therefore increasing efficiency
*Programmers have control of memory organisation.
Disadvantages of Von neumann Architecture.
*Parallel executions of programs are not allowed due to serial instruction processing
*Only one “bus” can be accessed at a time. This results in the CPU being idle (as it’s faster than a data bus) This is considered to be thevon Neumann Bottleneck.
*Although both instructions and data being stored in the same place can be viewed as an advantage as a whole. This can however result in re-writing over it, which results in data loss, due to an error in a program
Characteristics of the Harvard Architecture.
*Keeps instructions and data in SEPERATE memory.
*Processor accesses memory using SEPERATE data and address buses.
Advantages of Harvard Architecture.
*Due to instructions and data being transferred in different buses, this means there is a smaller chance of data corruption.
*Instructions and data can be accessed the same way
*Harvard architecture offers a high performance, as this architecture allows a simultaneous flow of data and instructions. These are kept in a separate memory and travel via separate buses
*There is a greater memory bandwidth that is more predictable, due to the architecture having separate memory for instructions and data
Disadvantages of Harvard.
*The memory dedicated to each (data and instructions) must be balanced by the manufacturer.
*This architecture, however, despite the high performance, is very complex, especially for main board manufacturers to implement
What is Contemporary Architecture?
Modern high performance CPU chips incorporate aspects of both Von Neumann and Harvard Architecture
Example
*A main memory may hold both data and instructions BUT *The cache may be divided into instruction and data cache *The Harvard architecture is used for accessing Cache
What is an instruction set?
The set of all instructions written in machine code that can be recognised and executed by a given processing unit.
What is a CISC processor?
Complex Instruction set computer
*Execute complex instructions in as few lines of assembly as possible.
*Many low level operations as a part of a single instruction.
*less space in the main memory taken and easier to translate code to machine code.
*Difficult to implement piplining.
*may take more than one clock cycle to execute.
What is a RISC Processor?
Reduced instruction set computer.
*One instruction is carried out per system clock cycle.
*More RAM is needed to store assembly instructions and compiler needs to do more conversion work.
*Hardware is less complex so less transisters are needed leaving rooms for cache and general purpose registers for performance.
*Uniform instructions means we can use piplining.
*Lower energy requirement.
*For portable devices.
What is a GPU?
*A GPU is a form of a Co-Processor.
*GPU :- Graphical Processing Unit
*They are great at large numbers of calculations in parallel so it can handle Graphics calculations that are needed.
*They take advantage of parallel processing.
*Used in :-machine learning, image processing, financial transactions, weather modelling, statistical analysis, stoch option predictions.
What is a Co-Processor?
Any additional processor used for a specialised task, to improve overall speed of the computer by working alongside the main CPU
