Paging Flashcards

1
Q

What is paging?

A

The process of splitting physical memory into equal sized blocks.

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2
Q

Page

A

A virtual block.

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3
Q

Process Address Space

A

Set of logical addresses that a process references in its code.

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4
Q

Process Memory Addresses Locations

A

Will appear as one contiguous range in process address space, but in reality they are multiple pages that could be anywhere in physical memory.

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5
Q

Page Frame

A

The physical memory used by a page.

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6
Q

Page Table

A

Each process has a page table that maps a logical page onto a physical memory frame, and needs to be stored into memory as a part of the process image. The address is stored in the page table base register within the CPU.

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7
Q

Virtual Addresses

A

Split into high part (stores an index into page table) and low part (stores the offset into the physical page frame).

Lets say we have 4 pages in process address space, with process memory addresses 0 to 3. The page table would assign these indexes to wherever they are in physical memory.
We could have the 0th page matching to the 7th frame/index in memory, for example.
Now lets say we want a specific part in the 0th page, which is four bits. The 1st index of the page contains the information we need. So we then look at the high part of the virtual address, aka the first half of the bits, which gives us the index of the virtual page. Taking this index, we look at the page table, and whatever the index assigns to is the position of the frame the page maps to, aka 7.

We then look at the low part of the virtual address, aka the second half of the bits, which is the index within the frame. We look for the index, and retrieve the data from it.

The virtual address could then look like this in a 8 bit system: 00010111. 0001 represents 1, the index of the virtual page, and 0111 represents the index of the data in the frame.

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8
Q

Paging vs. Segmentation

A

Memory allocation is much easier with fixed size (pages), and fragmentation is eliminated.

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9
Q

Segmentation with Paging

A

Intel x86 MMU supports segmentation with paging, in which:
- process memory is split into logical segments
- segments are stored within pages
This allows the logical segments with the advantages of fixed sizes.

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10
Q

Page Swapping/ Paging Out

A

Pages being stored on disk when there is too much allocation of memory. If a process tries to access a page in main memory, however, a page fault occurs since the page is on the disk. So an interrupt is sent, which an interrupt handler catches, resulting in the page being loaded from disk.

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11
Q

Page Swapping Techniques

A

Least Recently Used
First In First Out
Least Frequently Used
Second Chance -> uses FIFO but keeps pages that were recently used.

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12
Q

Principle of Locality

A

“Over any soft period of time, a process’s memory references tend to be spatially localised” which means that memory addresses that a process refers to in the next time period are likely to be close to addresses used in the current period. This helps guessing the next memory address easier for processes that frequently come back.

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13
Q

POL Determined Results

A
  • instructions don’t usually jump all over the place.
  • code within a loop spends tie in same area
  • accessing an array or other data structure will be around same area
    A general rule of thumb is that execution stays within 20% of a process’s pages for 80% of the time.
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14
Q

Working Set

A

The set of pages W(T, s) used in the time period from T to T + s (refer to Principle of Locality).

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15
Q

Working Set Accuracy

A

The accuracy depends if it is too big (will cover several localities and therefore the predictions won’t matter as much since it is just a bigger area) or too small (the prediction is way too concise, and won’t come true as much)

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16
Q

Page Size

A

Larger pages = smaller page table since there will be less entries, and vice versa.
Larger pages = more final pages that won’t be entirely full, losing around 50% of a page due to internal fragmentation.
Smaller pages = better use of memory and swap space, with decreased fragmentation
Smaller pages = higher chance of page faults, and more pages being swapped

17
Q

Cache Memory

A

Small, fast memory between CPU and main memory which contains frequently used data copies from main memory so they can be accessed faster.
Device controllers may also have their own cache memory.

18
Q

Cache Hits and Misses

A

Hit -> checking if data is in cache and it is, making it the most frequently used.
Miss -> checking if data is in cache and it is not, resulting it being fetched from memory and replaced with least frequently used data.

19
Q

Cache Levels

A

Small/fast cache - L1
Bigger, slower cache - L2 and L3