P3L4 - Synchronization Constructs Flashcards
Why do you need synchronization constructs OTHER than simple mutexes and condition variables?
They are not error proof!
____ is one of the most basic synchronization constructs?
Spinlock
What is the purpose of a spinlock?
To provide mutual exclusion
How are spinlocks different from mutexes since both provide mutual exclusion?
When a spinlock is locked, and a thread is attempting to lock it, the thread is NOT blocked. The thread is spinning (running on the CPU repeatedly checking to see if the lock has become free)
What is the use of semaphores?
To express COUNT RELATED synchronization requirements
What are semaphores initialized with?
An integer value
What happens if thread arrives at a semaphore with a value of 0
It blocks
What happens if a thread arrives at a semaphore with a nonzero value?
It decrements the value and proceeds with execution
What do you call a semaphore initialized with a 1
A binary semaphore - Will only allow one thread at a time to pass
_____ is a construct that behaves similarly to a mutex but requires that the user only specify the type of access they wish to perform
Read/Write lock
What is an alternative name for read/write locks?
Shared/Exclusive locks
T/F: Some implementations allow readers to convert their lock into a writer lock mid-execution?
True!
____ are a higher level synchronization construct that allow us to avoid manually invoking lock/unlock operations
Monitors
T/F: We need the checking of the lock value and the setting of the lock value to happen atomically
True - We need to be able to guarantee that only one thread a time can successfully obtain the lock
List some examples of atomic operations?
- test_and_set
- read_and_increment
- compare_and_swap
What does it mean to say that an operation is atomic?
It will happen completely or not at all
What guarantees are made by the hardware for atomic instructions?
- That the operations will happen atomically
2. There will be mutual exclusion
What are the two types of memory configurations for multiprocessor systems?
- Interconnect based
2. Bus-Based
What is the main difference between bus based configuration and interconnect based configuration of memory?
In the interconnect-based configuration, multiple memory references can be in flight at a given moment whereas in the bus-based configuration the shared bus can only support one memory reference at a time
T/F: In general, access to the cache data is faster than access to data in main memory?
True
Define non-cache coherent architecture
If one CPU writes a new version to its cache, the hardware will NOT update the value across the other CPU caches
Define cache-coherent architectures
Hardware will take care of all the necessary steps to ensure that the caches are coherent
What are the two basic strategies by which the hardware can achieve cache coherence?
- Write-Invalidate
2. Write-Update
_____ strategy will invalidate all cache entries once one CPU updates its copy. Future references to invalidated cache entries will have to pass through to main memory before being re-cached
Write-Invalidate
