P3L4 - Synchronization Constructs

Question 1

Why do you need synchronization constructs OTHER than simple mutexes and condition variables?

Answer 1

They are not error proof!

Question 2

____ is one of the most basic synchronization constructs?

Answer 2

Spinlock

Question 3

What is the purpose of a spinlock?

Answer 3

To provide mutual exclusion

Question 4

How are spinlocks different from mutexes since both provide mutual exclusion?

Answer 4

When a spinlock is locked, and a thread is attempting to lock it, the thread is NOT blocked. The thread is spinning (running on the CPU repeatedly checking to see if the lock has become free)

Question 5

What is the use of semaphores?

Answer 5

To express COUNT RELATED synchronization requirements

Question 6

What are semaphores initialized with?

Answer 6

An integer value

Question 7

What happens if thread arrives at a semaphore with a value of 0

Answer 7

It blocks

Question 8

What happens if a thread arrives at a semaphore with a nonzero value?

Answer 8

It decrements the value and proceeds with execution

Question 9

What do you call a semaphore initialized with a 1

Answer 9

A binary semaphore - Will only allow one thread at a time to pass

Question 10

_____ is a construct that behaves similarly to a mutex but requires that the user only specify the type of access they wish to perform

Answer 10

Read/Write lock

Question 11

What is an alternative name for read/write locks?

Answer 11

Shared/Exclusive locks

Question 12

T/F: Some implementations allow readers to convert their lock into a writer lock mid-execution?

Answer 12

True!

Question 13

____ are a higher level synchronization construct that allow us to avoid manually invoking lock/unlock operations

Answer 13

Monitors

Question 14

T/F: We need the checking of the lock value and the setting of the lock value to happen atomically

Answer 14

True - We need to be able to guarantee that only one thread a time can successfully obtain the lock

Question 15

List some examples of atomic operations?

Answer 15

1. test_and_set
2. read_and_increment
3. compare_and_swap

Question 16

What does it mean to say that an operation is atomic?

Answer 16

It will happen completely or not at all

Question 17

What guarantees are made by the hardware for atomic instructions?

Answer 17

1. That the operations will happen atomically

2. There will be mutual exclusion

Question 18

What are the two types of memory configurations for multiprocessor systems?

Answer 18

1. Interconnect based

2. Bus-Based

Question 19

What is the main difference between bus based configuration and interconnect based configuration of memory?

Answer 19

In the interconnect-based configuration, multiple memory references can be in flight at a given moment whereas in the bus-based configuration the shared bus can only support one memory reference at a time

Question 20

T/F: In general, access to the cache data is faster than access to data in main memory?

Answer 20

True

Question 21

Define non-cache coherent architecture

Answer 21

If one CPU writes a new version to its cache, the hardware will NOT update the value across the other CPU caches

Question 22

Define cache-coherent architectures

Answer 22

Hardware will take care of all the necessary steps to ensure that the caches are coherent

Question 23

What are the two basic strategies by which the hardware can achieve cache coherence?

Answer 23

1. Write-Invalidate

2. Write-Update

Question 24

_____ strategy will invalidate all cache entries once one CPU updates its copy. Future references to invalidated cache entries will have to pass through to main memory before being re-cached

Answer 24

Write-Invalidate

Question 25

_____ strategy will ensure that all cache entires are updated once one CPU updates its copy

Answer 25

Write-Update

Question 26

T/F: Atomic instructions on SMP are more expensive than on single CPU systems because of bus or I/C contention?

Answer 26

True!