P3L2: Memory Management Flashcards
What are three guiding principles of Memory Management system?
- Intelligently sized containers: The size of memory pages and segments is an important design consideration.
- Not all memory is needed at once: Tasks operate on a subset of memory.
- Optimize for performance: Reducing the time needed to access memory improves performance.
What are the three tasks of memory management? (What does mem mgmt DO?)
- Manage physical memory (DRAM) on behalf of executing processes. We do this by decoupling physical from virtual addresses.
- Allocate physical memory: track how it’s used and what’s free, determine what should be stored in memory and what can be moved to disk
- Arbitrate: OS needs to perform translation from virtual to physical address and validate it.
Describe page-based memory management
- The virtual address space is divided into fixed-sized segments called pages.
- Physical memory is divided into page frames of the same size.
- Allocation is then about mapping pages to page frames
- Arbitration is accomplished via page tables
(this is the most common method)
Describe segment-based memory management
- Allocation is accomplished using flexibly-sized segments which can be mapped to regions of physical memory or swapped in and out of physical memory
- Arbitration is accomplished using segment registers
(this is less common than page-based mem mgmt)
How does hardware support memory management?
- Memory management units
- Registers
- Translation Lookaside Buffer
What is the memory management unit?
- Equipped on the CPU package
- Translates virtual to physical addresses
- Generates faults: illegal access, inadequate permissions, requested page isn’t present in memory
How are hardware registers used in the address translation process?
- Page-based system: Register points to currently active page table
- Segment-based system: Register stores the base address of segments, limit address (size) of segment, number of segments
Describe the Translation Lookaside Buffer
The TLB is a hardware cache of valid virtual to physical address translations. This avoids the need to perform translation and speeds things up.
What performs translation of virtual to physical addresses, hardware or software? How does this affect the design of memory management system?
Hardware! The hardware therefore dictates what kinds of memory management are supported (paging vs segment, what kind of pages, etc.)
What performs allocation of memory, hardware or software? What does this mean for design of mm system?
Software! This means the system can be more flexible.
What performs replacement policy for memory management, hardware or software?
Software! This makes it more flexible.
What are page tables and how do they work?
- Page tables intermediate between virtual memory addresses (pages) and physical memory, translating one to the other.
- Because the virtual pages and physical page frames are the same size, the page table only has to map the first virtual address in each page to the first physical address in each page frame.
Describe the mapping of virtual to physical addresses via the page table
Because we only need to map the first entry in each page to the first entry in each page frame, the page table only requires the Virtual Page Number (VPN), i.e., the first part of the virtual address.
We use the VPN as an offset in the page table to find the Physical Frame Number (PFN).
Once we have that, we append the remainder of the virtual address after the VPN (the offset) to the PFN.
What is “allocation on first touch”?
This means that we only allocate physical memory to an object when we first try to access it. This prevents the allocation of physical memory to objects that are never used.
What happens when pages go unused for a long time?
The associated physical page frames are reclaimed and eventually reassigned to other pages. The data stored in the page frame is pushed to disk.
How do page tables help detect reclaimed page frames?
In addition to the mapping from VPN to PFN, the page table also includes bits that tell the mem mgmt system info about the validity of an attempted access.
If the page is in physical memory, the bit is 1, otherwise 0.
If MMU sees that bit is zero, it will raise a fault and the OS will take over and decide how to handle it.
As long as this was a valid address is being accessed, the data will be brought back into physical memory, likely at a different location. Page map is updated.
How many page tables are maintained?
One per process
How are page tables involved in a context switch?
On a context switch to a new process, the OS must switch to the page table for that process.
Describe a generic page table entry
A page table entry will include:
- Page frame number ( PFN)
- Valid bit (also called present bit): indicates whether page is in memory
- Dirty bit: indicates whether a page has been written to. Useful in file caching.
- Access bit: has the page been read or written to?
- Protection bits (RWX): Can indicate that page is only readable, only writable, or some other kind of access
What is the common page size?
4kb
Describe the storage issue for page tables
Page table has n entries, where n is the number of virtual page numbers in virtual address space. Each entry holds PFN + flags, 8 bytes oughtta do it for 64-bit arch.
The number of entries depends on the size of the addresses and page size. On 64-bit architecture with 4 kb pages, that means 2^64 / 4 kb = 2^64 / 2^12 = 2^52 entries. If each entry is 8 bytes long, that’s 2^52 * 8 bytes = 32 PB!
Per process!
