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NEETS > NEETS 13 CH 3 > Flashcards

NEETS 13 CH 3 Flashcards

1
Q

What is the sign of operation for the X-OR gate?

A

⊕.

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2
Q

What will be the output of an X-OR gate when both inputs are HIGH?

A

Low (0).

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3
Q

A two-input X-OR gate will produce a HIGH output when the inputs are at what logic levels?

A

One or the other of the inputs must be HIGH, but not both at the same time.

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4
Q

What type of gate is represented by the output Boolean expression T ⊕R ?

A

Exclusive NOR (X-NOR).

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5
Q

What will be the output of an X-NOR gate when both inputs are LOW?

A

HIGH.

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6
Q

What advantage does a half adder have over a quarter adder?

A

The half adder generates a carry.

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7
Q

An X-OR gate may be used as what type of adder?

A

Quarter adder.

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8
Q

What will be the output of a half adder when both inputs are 1s?

A

Sum equals 0 with a carry of 1.

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9
Q

What type of adder is used to handle a carry from a previous circuit?

A

Full adder.

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10
Q

How many full adders are required to add four-digit numbers?

A

Four.

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11
Q

With the inputs shown below, what will be the output of S1, S2, and C2?

A

S1 = 1, S2 = 0 and C2 = 1.

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12
Q

What is the output of C1?

A

C1 = 0

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13
Q

What type of logic gates are added to a parallel adder to enable it to subtract?

A

X-OR gates.

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14
Q

How many of these gates would be needed to add a four-digit number?

A

Four.

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15
Q

In the add mode, what does the output of C2 indicate?

A

MSD of the sum.

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16
Q

In the subtract mode, a 1 at C0 performs what portion of the R’s complement?

A

Add 1 portion.

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17
Q

In the subtract mode, which portion of the problem is complemented?

A

Subtrahend.

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18
Q

What are R-S FFs used for?

A

Storing information.

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19
Q

How many R-S FFs are required to store the number 1001012?

A

Six.

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20
Q

For an R-S FF to change output conditions, the inputs must be in what states?

A

1 and 0, or opposite states.

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21
Q

How may R-S FFs be constructed?

A

By cross-coupling NAND or OR gates.

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22
Q

How many inputs does a T FF have?

A

One.3-45

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23
Q

What is the purpose of using T FFs?

A

To divide the input by 2

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24
Q

What are the inputs to a D FF?

A

Clock and data.

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25
Q

How long is data delayed by a D FF?

A

Up to one clock pulse.

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26
Q

What condition must occur to have a change in the output of a D FF?

A

A positive-going clock pulse.

27
Q

What type of FF can be used as an R-S, a T, or a D FF?

A

J-K flip-flop.

28
Q

What will be the output of Q if J is HIGH, PS and CLR are HIGH, and the clock is going negative?

A

Set, or HIGH (1).

29
Q

Assume that K goes HIGH and J goes LOW; when will the FF reset?

A

When the clock pulse goes LOW.

30
Q

What logic levels must exist for the FF to be toggled by the clock?

A

Both J and K must be HIGH.

31
Q

What two inputs to a J-K FF will override the other inputs?

A

Clear (CLR) and preset (PS or PR).

32
Q

How is the J-K FF affected if PS and CLR are both LOW?

A

The flip-flop is jammed.

33
Q

What is a clock with regard to digital equipment?

A

A timing signal.

34
Q

What is the simplest type of clock circuit?

A

An astable or free-running multivibrator.

35
Q

What is needed to use a monostable or one-shot multivibrator for a clock circuit?

A

Triggers

36
Q

What type of clock is used when more than one operation is to be completed during one clock cycle?

A

A multiphase clock

37
Q

What is the modulus of a five-stage binary counter?

A

32

38
Q

An asynchronous counter is also called a ___________ counter

A

Ripple.

39
Q

J-K FFs used in counters are wired to perform what function?

A

Toggle.

40
Q

What type of counter has clock pulses applied to all FFs?

A

Synchronous.

41
Q

In figure 3-24, view A, what logic element enables FF3 to toggle with the clock?

A

The AND gate.

42
Q

What is the largest count that can be indicated by a four-stage counter?

A

11112, or 1510.

43
Q

How many stages are required for a decade counter?

A

Four

44
Q

In figure 3-25, which two FFs must be HIGH to reset the counter?

A

FFs 2 and 4.

45
Q

In figure 3-26, view A, which AND gate causes FF3 to set?

A

Two

46
Q

Which AND gate causes FF3 to reset?

A

Three.

47
Q

What causes the specified condition to shift position?

A

The input, or clock pulse.

48
Q

If the specified state is OFF, how many FFs may be off at one time?

A

One.

49
Q

How many FFs are required to count down from 1510?

A

Four.

50
Q

What signal causes FF2 to toggle?

A

Q output of FF 1 going LOW.

51
Q

How many stages are required to store a 16-bit word?

A

. 16.

52
Q

Simultaneous transfer of data may be accomplished with what type of register?

A

Parallel

53
Q

How are erroneous transfers of data prevented?

A

By clearing the register.

54
Q

Serial-to-parallel and parallel-to-serial conversions are accomplished by what type of circuit?

A

Shift register.

55
Q

What type of data transfer requires the most time?

A

Serial

56
Q

What is the main disadvantage of parallel transfer?

A

Requires more circuitry.

57
Q

How many FFs would be required for an 8-bit shift register?

A

Eight.

58
Q

How many clock pulses are required to output a 4-bit number in serial form?

A

Four

59
Q

Two shifts to the left are equal to increasing the magnitude of a number by how much?

A

22, or four times.

60
Q

To increase the magnitude of a number by 23, you must shift the number how many times and in what direction?

A

Three to the left.

61
Q

What are RTL, DTL, and TTL examples of?

A

Logic families

62
Q

What type of logic family uses diodes in the input?

A

DTL (diode transistor logic).

63
Q

What is the most common type of integrated circuit packaging found in military equipment?

A

DIPs (dual inline packages).

64
Q

Circuits that can be interconnected without additional circuitry are known as ____________ circuits.

A

Compatible.

NEETS (11 decks)

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