NEETS 13 CH 3 Flashcards
What is the sign of operation for the X-OR gate?
⊕.
What will be the output of an X-OR gate when both inputs are HIGH?
Low (0).
A two-input X-OR gate will produce a HIGH output when the inputs are at what logic levels?
One or the other of the inputs must be HIGH, but not both at the same time.
What type of gate is represented by the output Boolean expression T ⊕R ?
Exclusive NOR (X-NOR).
What will be the output of an X-NOR gate when both inputs are LOW?
HIGH.
What advantage does a half adder have over a quarter adder?
The half adder generates a carry.
An X-OR gate may be used as what type of adder?
Quarter adder.
What will be the output of a half adder when both inputs are 1s?
Sum equals 0 with a carry of 1.
What type of adder is used to handle a carry from a previous circuit?
Full adder.
How many full adders are required to add four-digit numbers?
Four.
With the inputs shown below, what will be the output of S1, S2, and C2?
S1 = 1, S2 = 0 and C2 = 1.
What is the output of C1?
C1 = 0
What type of logic gates are added to a parallel adder to enable it to subtract?
X-OR gates.
How many of these gates would be needed to add a four-digit number?
Four.
In the add mode, what does the output of C2 indicate?
MSD of the sum.
In the subtract mode, a 1 at C0 performs what portion of the R’s complement?
Add 1 portion.
In the subtract mode, which portion of the problem is complemented?
Subtrahend.
What are R-S FFs used for?
Storing information.
How many R-S FFs are required to store the number 1001012?
Six.
For an R-S FF to change output conditions, the inputs must be in what states?
1 and 0, or opposite states.
How may R-S FFs be constructed?
By cross-coupling NAND or OR gates.
How many inputs does a T FF have?
One.3-45
What is the purpose of using T FFs?
To divide the input by 2
What are the inputs to a D FF?
Clock and data.
How long is data delayed by a D FF?
Up to one clock pulse.
What condition must occur to have a change in the output of a D FF?
A positive-going clock pulse.
What type of FF can be used as an R-S, a T, or a D FF?
J-K flip-flop.
What will be the output of Q if J is HIGH, PS and CLR are HIGH, and the clock is going negative?
Set, or HIGH (1).
Assume that K goes HIGH and J goes LOW; when will the FF reset?
When the clock pulse goes LOW.
What logic levels must exist for the FF to be toggled by the clock?
Both J and K must be HIGH.
What two inputs to a J-K FF will override the other inputs?
Clear (CLR) and preset (PS or PR).
How is the J-K FF affected if PS and CLR are both LOW?
The flip-flop is jammed.
What is a clock with regard to digital equipment?
A timing signal.
What is the simplest type of clock circuit?
An astable or free-running multivibrator.
What is needed to use a monostable or one-shot multivibrator for a clock circuit?
Triggers
What type of clock is used when more than one operation is to be completed during one clock cycle?
A multiphase clock
What is the modulus of a five-stage binary counter?
32
An asynchronous counter is also called a ___________ counter
Ripple.
J-K FFs used in counters are wired to perform what function?
Toggle.
What type of counter has clock pulses applied to all FFs?
Synchronous.
In figure 3-24, view A, what logic element enables FF3 to toggle with the clock?
The AND gate.
What is the largest count that can be indicated by a four-stage counter?
11112, or 1510.
How many stages are required for a decade counter?
Four
In figure 3-25, which two FFs must be HIGH to reset the counter?
FFs 2 and 4.
In figure 3-26, view A, which AND gate causes FF3 to set?
Two
Which AND gate causes FF3 to reset?
Three.
What causes the specified condition to shift position?
The input, or clock pulse.
If the specified state is OFF, how many FFs may be off at one time?
One.
How many FFs are required to count down from 1510?
Four.
What signal causes FF2 to toggle?
Q output of FF 1 going LOW.
How many stages are required to store a 16-bit word?
. 16.
Simultaneous transfer of data may be accomplished with what type of register?
Parallel
How are erroneous transfers of data prevented?
By clearing the register.
Serial-to-parallel and parallel-to-serial conversions are accomplished by what type of circuit?
Shift register.
What type of data transfer requires the most time?
Serial
What is the main disadvantage of parallel transfer?
Requires more circuitry.
How many FFs would be required for an 8-bit shift register?
Eight.
How many clock pulses are required to output a 4-bit number in serial form?
Four
Two shifts to the left are equal to increasing the magnitude of a number by how much?
22, or four times.
To increase the magnitude of a number by 23, you must shift the number how many times and in what direction?
Three to the left.
What are RTL, DTL, and TTL examples of?
Logic families
What type of logic family uses diodes in the input?
DTL (diode transistor logic).
What is the most common type of integrated circuit packaging found in military equipment?
DIPs (dual inline packages).
Circuits that can be interconnected without additional circuitry are known as ____________ circuits.
Compatible.
