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Question 1

Race condition

Answer 1

خيطين او اكثر يحاولون يعدلون بيانات معينه بنفس الوقت بدون جدولة زمنية يؤدي الى نتايج غير متوقعه وحدوث اخطاء

Question 2

Critical section

Answer 2

منطقة من البرنامج تمنع اي تدخل اخر بنفس الوقت تفاديا لوقوع race condition او نتايج غير متوقعه

Question 3

Mutual exclusion

Answer 3

ميكانيزم تؤكد حدوث او وصول ثريد واحد لاداء فعل معين بوقت معين بترتيب

Question 4

Can a semaphore go below zero

Answer 4

No if a thread is executed when S is at 0 am he thread is blocked
It can run again if V(S) happens

Question 5

Deadlock

Answer 5

A situation when two or more processes wait in an infinite loop for an even that will not happen

Question 6

Register that controls different modes of operation in cpu

Answer 6

PSW (program status word)

Question 7

Machine code running while CPU is in____can only use limited instructions (no IN or OUT instructions)

Answer 7

User mode

Question 8

Only code running in ______ can use privilged instructions like IN and OUT

Answer 8

Kernel mode

Question 9

Instructions restricted in kernel mode

Answer 9

Instructions to change machine status mode
Instructions that perform I/O operations (IN,OUT)
Instructions that define interrupt handler

Question 10

RISC Instructions are the sane length

Answer 10

MIPS are all 4 bytes long
Pentium may be 1,2,3 or more

Question 11

RISC processor has a large number of general purpose registers

Answer 11

MIPS has 32 registers
Pentium has about 4

Question 12

RISC arithmetic instructions operate on register values

Answer 12

MIPS arithmetic take two registers as operands and put results in another register

In pentium add instructions operands or results can be registers or memory

Question 13

ALU

Answer 13

Arithmetic Logic Unit

Question 14

PC

Answer 14

Program Counter
Special purpose register that points instructions

Question 15

MIPS instruction

Answer 15

add=add instruction
Accessing memory = load word(lw)
Branching = branch on equal (beq)

Question 16

ARM

Answer 16

advanced RISC machine

Question 17

MIPS

Answer 17

Microprocessor without interlocked pipeline

Question 18

RISC

Answer 18

Reduced instruction set computers
تعليمات اقل = اكثر بساطة

Question 19

CISC

Answer 19

Complex instructions set computers
C stands for complex = اكثر تعقيد

Question 20

ISA

Answer 20

Instruction set architecture

Question 21

MIPS INSTRUCTION

Answer 21

Funct = function code
Shamt = shift amount
rd = register gets result
rs = first register
rt = second register
op = basic operation

Question 22

Process stages

Answer 22

المربع الازرق = جلب التعليمات fetching instructions
الهرم الازرق = تطبيق الامر execution
المربع البرتقالي = بيانات memory
الاخضر قسمين
اليمين يقرا = اليسار يكتب

Question 23

ILP

Answer 23

Instruction level parallelism