Multiprocessors Interconnection Networks Flashcards
Two Types of Bus-based Dynamic Interconnection Networks
Single Bus Systems and Multiple Bus Systems
generally consists of N processors, each having its own cache, connected by a shared bus; Use of local caches reduces the processor-memory traffic.
Single Bus Systems
A multiple bus multiprocessor system uses several parallel buses to interconnect multiple processors and multiple memory modules
Multiple Bus Systems
What are the 4 Possible connections of a multiple bus systems
Multiple Bus with Full Bus-Memory Connection (MBFBMC), Multiple Bus with Single Bus-Memory Connection (MBSBMC), Multiple Bus with Partial Bus-Memory Connection (MBPBMC), Multiple Bus with Class-based Memory Connection (MBCBMC)
Formula for counting the number of connections in a Multiple Bus with Full Bus-Memory Connection (MBFBMC)
B(N+M), where B is the no. of buses, N is no. of processors, M is no. of memory banks.
Formula for calculating the “load on bus i” in a Multiple Bus with Full Bus-Memory Connection (MBFBMC)
N+M, where N is no. of processors, M is no. of memory banks.
Formula for counting the number of connections in a Multiple Bus with Single Bus-Memory Connection (MBSBMC)
BN+M, where B is the no. of buses, N is no. of processors, M is no. of memory banks.
Formula for calculating the “load on bus i” in a Multiple Bus with Single Bus-Memory Connection (MBSBMC)
N+Mj, where N is no. of processors, Mj is no. of memory modules in class j.
Since this type of connection does not have a class, each memory will be its own class. Thus, Mj = 1
Formula for counting the number of connections in a Multiple Bus with Partial Bus-Memory Connection (MBPBMC)
B(N+M/g), where B is the no. of buses, N is no. of processors, M is no. of memory banks, g is the no. of buses per group.
Formula for calculating the “load on bus i” in a Multiple Bus with Partial Bus-Memory Connection (MBPBMC)
N+M/g, where N is no. of processors, M is no. of memory banks, g is the no. of buses per group.
One of the well-known Multi-Staged Interconnection Networks
The Banyan Network
Formula for the No. of MIN stages in a Banyan Network
log2 (N)
, where N is the number of memory modules
Formula for the No. of switching element per stage in a Banyan Network
N/2, where N is the number of memory modules
Formula for the total no. of switching element in a Banyan Network; Is also the network complexity
N * log2 (N)
or O(N log2 N)
, where N is the number of memory modules
Formula for the no. of switching elements along the path from input to output; Is also the time complexity
log2 (N)
or O(log2 N)
, where N is the number of memory modules