MOSFET as a switch

Question 1

How are enhancement-mode MOSFETs denoted on a circuit diagram?

Answer 1

Dotted line

Question 2

What is a depletion mode MOSFET?

Answer 2

It has a negative pinch off voltage. Vgs << 0

Question 3

How are depletion mode MOSFETs denoted on a circuit diagram?

Answer 3

Solid line at the junction

Question 4

What is the convention with digital logic circuits?

Answer 4

Two states (1 & 0) 0 = 0V ≈ <1V 1 = 8V ≈ >7V

Question 5

How can you turns a FET into a switch?

Answer 5

See image:

Question 6

What happens when the input to this circuit is connected to gound? (The MOSFET is an enhancement-mode MOSFET)

Answer 6

When the input is 0V, Vgs = 0 so this means that current will not flow and so the output Q is connected to 8V.

Question 7

What happens when the input to this circuit is HIGH? (The MOSFET is an enhancement-mode MOSFET)

Answer 7

This will make Vgs = 8V allowing current to flow through the transistor. This connects the output Q to ground so the output is low.

Question 8

With regards to the logic circuit that turns a FET into a switch describe the graph.

Answer 8

When Vgs = 0, the drain source voltage is at 8V becuase the output is being connected to 8V as no current if flowing throught the transistor so Vds is high.

When Vgs = 8V (blue line) the drain current is high and drain source voltage is low because the output is being connected to ground.

Question 9

Summarise the properties of the circuit:

Answer 9

When:

Input = Low ⇒ Ouput = HIgh

Input = High ⇒ Output = Low

Question 10

How is an AND gate made from switches?

Answer 10

2 Switches in series

Question 11

How is an OR gate made from swtiches?

Answer 11

Two swtiches in parrallel

Question 12

What is the configuarion of a NOR gate made with transistors?

Answer 12

Question 13

What is the configuration of a NAND gate made from transistors?

Answer 13

Question 14

What is a CMOS gate?

Answer 14

This is a type of gate using 2 types of CMOS transisotrs.

Question 15

What are the 2 CMOS transistor types?

Describe them.

Answer 15

P - channel: Vgs < 0 ⇒ for current to pass

N - channel: Vgs > 0 ⇒ for current to pass

Question 16

What is the layout of a CMOS NOT gate?

Answer 16

Remember the directions of the Sources and Drains of the transistors!!!

Question 17

How does a CMOS NOT gate work?

Answer 17

When input (A) is high:

P-channel: Vgs = 0 ⇒ Open

N-channel: Vgs = 8 ⇒ Closed

This connects the output to ground.

When input (A) is low:

P-channel: Vgs = -8 ⇒ Closed

N-channel: Vgs = 0 ⇒ Open

This connects the output to ground.

Question 18

What happens to a CMOS NOT gate if the input (A) has a voltage of 4V?

Answer 18

Both of the transistors are in the conducting region so current flows from Vdd to Gnd and this can damage the transistors.

Question 19

What is the arrangement for CMOS transistors in a CMOS NOR gate?

Answer 19

NOR ⇒ NOT ⇒ NOT

The use to the 2 not gates is as a buffer stage

Question 20

What is the arrangement for CMOS transisotrs in a NAND gate?

Answer 20

NAND ⇒ NOT ⇒ NOT

The two NOT gates are buffer stages

Question 21

Why do tracks on a PCB for a computer often Zig-Zag?

Answer 21

This is becyase if the tracks are different lengths, then at high frequencies propagation delay may cause bits to arrive at different times. Changing the track lengths can compensate for this.