MOSFET as a switch Flashcards
How are enhancement-mode MOSFETs denoted on a circuit diagram?
Dotted line
What is a depletion mode MOSFET?
It has a negative pinch off voltage. Vgs << 0
How are depletion mode MOSFETs denoted on a circuit diagram?
Solid line at the junction
What is the convention with digital logic circuits?
Two states (1 & 0) 0 = 0V ≈ <1V 1 = 8V ≈ >7V
How can you turns a FET into a switch?
See image:
What happens when the input to this circuit is connected to gound? (The MOSFET is an enhancement-mode MOSFET)
When the input is 0V, Vgs = 0 so this means that current will not flow and so the output Q is connected to 8V.
What happens when the input to this circuit is HIGH? (The MOSFET is an enhancement-mode MOSFET)
This will make Vgs = 8V allowing current to flow through the transistor. This connects the output Q to ground so the output is low.
With regards to the logic circuit that turns a FET into a switch describe the graph.
When Vgs = 0, the drain source voltage is at 8V becuase the output is being connected to 8V as no current if flowing throught the transistor so Vds is high.
When Vgs = 8V (blue line) the drain current is high and drain source voltage is low because the output is being connected to ground.
Summarise the properties of the circuit:
When:
Input = Low ⇒ Ouput = HIgh
Input = High ⇒ Output = Low
How is an AND gate made from switches?
2 Switches in series
How is an OR gate made from swtiches?
Two swtiches in parrallel
What is the configuarion of a NOR gate made with transistors?
What is the configuration of a NAND gate made from transistors?
What is a CMOS gate?
This is a type of gate using 2 types of CMOS transisotrs.
What are the 2 CMOS transistor types?
Describe them.
P - channel: Vgs < 0 ⇒ for current to pass
N - channel: Vgs > 0 ⇒ for current to pass
What is the layout of a CMOS NOT gate?
Remember the directions of the Sources and Drains of the transistors!!!
How does a CMOS NOT gate work?
When input (A) is high:
P-channel: Vgs = 0 ⇒ Open
N-channel: Vgs = 8 ⇒ Closed
This connects the output to ground.
When input (A) is low:
P-channel: Vgs = -8 ⇒ Closed
N-channel: Vgs = 0 ⇒ Open
This connects the output to ground.
What happens to a CMOS NOT gate if the input (A) has a voltage of 4V?
Both of the transistors are in the conducting region so current flows from Vdd to Gnd and this can damage the transistors.
What is the arrangement for CMOS transistors in a CMOS NOR gate?
NOR ⇒ NOT ⇒ NOT
The use to the 2 not gates is as a buffer stage
What is the arrangement for CMOS transisotrs in a NAND gate?
NAND ⇒ NOT ⇒ NOT
The two NOT gates are buffer stages
Why do tracks on a PCB for a computer often Zig-Zag?
This is becyase if the tracks are different lengths, then at high frequencies propagation delay may cause bits to arrive at different times. Changing the track lengths can compensate for this.
