Module 8 - CPU Design Choices

Question 1

What is the maximum speedup (upper limit) of an N-stage pipelined processor?
  N/2
  N*N
  N
  4

Answer 1

N

Question 2

Question 2
1 / 1 pts
Pipelined processor designs increase performance, but at the cost of:
  Increased RAM utilization.
  Increased processor design complexity.
  Decreased heat output.
  Decreased clock rate.

Answer 2

Increased processor design complexity.

Question 3

The speedup of a pipelined processor is due to the:

Increased throughput.
Reduced latency of executing each instruction.
Reduced complexity of processor hardware.
Increased instruction count.

Answer 3

Increased throughput.

Question 4

Where do we save the control signals for different instructions in a pipelined datapath?
In the stack.
In the 32 floating-point registers.
In pipeline registers between the stages.
In the 32 integer registers

Answer 4

In pipeline registers between the stages.

Question 5

Pipeline registers store (select all that apply):

The results of pipeline stage execution
The instruction word in every stage of the pipeline
Control signals related to the instruction
Instruction data necessary for the execution of later stages.

Answer 5

The results of pipeline stage execution
Control signals related to the instruction
Instruction data necessary for the execution of later stages.

Question 6

Forwarding (bypassing) alone can completely avoid stall (bubble) caused by: (select all that apply)

  Arithmetic Instructions
  Load Instruction
  Store Instruction
  All Instructions
  Branching Instructions

Answer 6

Arithmetic Instructions

Question 7

What MIPS instruction will always cause a stall if the next instruction uses its result?
  BEQ
  SW
  Add
  LW

Answer 7

LW

Question 8

A branch instruction can cause a stall, because:
The memory read operation takes too long
Two instructions use the same memory address
The memory write operation takes too long
The address of the next instruction is unknown
It cannot cause a stall.

Answer 8

The address of the next instruction is unknown

Question 9

Which of the following techniques can reduce the effect of the hazards in this piece of code (Select all that apply):

lw $s1, 0($s0)
lw $s2, 4($s0)
add $s3, $s1, $s2
sw $s3, 12($s0)
lw $s4, 8($s0)
add $s5, $s1, $s4

  Branch Prediction
  Forwarding
  Early Decision
  Stall
  Overflow Handling

Answer 9

Forwarding

Stall

Question 10

What types of hazards does a pipelined processor need to deal with specifically? Select all that apply.
  Overflow Hazards
  Exceptions
  Structure Hazards
  Data Hazards
  Control Hazards

Answer 10

Structure Hazards
Data Hazards
Control Hazards

Question 11

Which of the following describes 1-bit history table branch prediction?
A history table is used to store multiple bits, mapped to the branch instruction address, indicating the history of the branch behavior. A state machine is used to update the table.
A history table is used to store a single bit mapped to the branch instruction address, indicating that the branch was previously taken or untaken.
The next instruction to load after a branch instruction is randomly chosen from instruction memory.
Hardware designer specifies to always predict a taken or untaken branch.

Answer 11

A history table is used to store a single bit mapped to the branch instruction address, indicating that the branch was previously taken or untaken.

Question 12

What is an advantage of a dynamic branch prediction method, like history table? (Select all that apply)

Increases hardware complexity.
High branch prediction accuracy (better than chance)
Low branch prediction accuracy (no better than chance).
Simple implementation.
Increased performance.

Answer 12

High branch prediction accuracy (better than chance)

Increased performance.

Question 13

Which of the following describes 2-bit history table branch prediction?
Hardware designer specifies to always predict a taken or untaken branch.
A history table is used to store multiple bits, mapped to the branch instruction address, indicating the history of the branch behavior. A state machine is used to update the table.
The next instruction to load after a branch instruction is randomly chosen from instruction memory.
A history table is used to store a single bit mapped to the branch instruction address, indicating that the branch was previously taken or untaken.

Answer 13

A history table is used to store multiple bits, mapped to the branch instruction address, indicating the history of the branch behavior. A state machine is used to update the table.

Question 14

What is a disadvantage of a dynamic branch prediction method, like history table? (Select all that apply)
Simple implementation.
High branch prediction accuracy (better than chance)
Increased performance.
Increases hardware complexity.
Low branch prediction accuracy (no better than chance).

Answer 14

Increases hardware complexity.

Question 15

Which of the following describes static branch prediction?

The next instruction to load after a branch instruction is randomly chosen from instruction memory.
A history table is used to store multiple bits, mapped to the branch instruction address, indicating the history of the branch behavior. A state machine is used to update the table.
Hardware designer specifies to always predict a taken or untaken branch.
A history table is used to store a single bit mapped to the branch instruction address, indicating that the branch was previously taken or untaken.

Answer 15

Hardware designer specifies to always predict a taken or untaken branch.