Module 6 Flashcards
What is parallel vs serial?
Parallel
- Multiple inputs taken at the same time
Serial
- Inputs taken on one line piece by piece
Big and Little Endian
Big Endian (normal)
- Stores the MSB first
Little Endian (weird)
- Stores the LSB first
Asynchronous vs Synchronous
Async has an agreed upon time for comms to take place in (UART) while sync is dependent on clock timers.
Simplex, Half Duplex, Full Duplex
Simplex
- One device Rx, one device Tx and the communication only goes from Tx to Tx
Half Duplex
- Both devices can Rx and Tx but there is only one comms channel
Full Duplex
- Both devices can Rx and Tx and there are two comms channels so that this can happen at the same time
What is the basic message structure
Start -> data -> stop
What is parity and how does the parity bit work
Parity is the number of 1s in a message.
Odd parity means there must be an odd number of 1s in the entire message (including the parity bit itself)
Even parity means there must be an even number of 1s in the entire message.
I2C Features and Operation
Half duplex
+ Simple, robust, cheap
+ Can have multiple masters and multiple slaves
- Use of ACK and NACK creates large overheads
Has features of arbitration and clock stretching
- Arbitration occurs when a two masters race to hold a line low. Whichever wins then gets to communicate
- Clock stretching occurs when a master holds the clock line low for longer than required to process more data.
Makes use of two wires, SCL and SDA.
- SCL is the clock
- SDA is the data line
The Transmission Process:
IDLE: Both SDA and SCL are high
START: SDA goes low while SCL remains high
STOP: SDA goes high while SCL remains high
The process then goes:
START -> ADDRESS -> RW -> DATA -> ACK and repeat
ACK = 0 and NACK = 1
SPI Features and Operation
4-wire full duplex system
!CS, MISO, MOSI, CLK
The master has control over the !CS which is active low and is used to connect to the slaves. There are two options for each of the SPI things: CPOL and CPHA
CPOL defines the clock: 0 means active low and 1 means active high
CPHA defines when signals are read based on the clock: 0 means read on the leading edge and 1 means read on the trailing edge
These two are often defined in SPI modes ranging from 0 to 3.
The master will pull !CS low to select a slave and communicate using it’s MOSI line. The slave will then respond with the MISO line simultaneously.
UART Features and Operation
UART is full duplex. UART is asynchronous - both devices require the same baud rate which is defined in 2^n * 150 regions.
The Rx and Tx lines start high. The default time unit is T which is equal to 1/BR. The Tx line is then pulled low for 1.5T s. Rx and Tx will the communicate using signals timed at 1T s until Tx goes high for 1.5T, at which point comms stop.
RS232 Features and Operation
RS232 sucks and no one likes it. It is full duplex and asynchronous like UART
Uses -3V to -15V as logic high and +3V to +15V as logic low. A MAX232 chip can be used to convert the [-3V,-15V] to 3.3V and [+3V,+15V] to 0V for comms with the STM32F0.
Only allows one transmitter bus and one receiver bus. Can only transmit over distances about 15m.
RS485 can transmit over 1200m and uses twisted cables to prevent interference.
