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CAO > Module 4 > Flashcards

Module 4 Flashcards

1
Q

What are the key characteristics of memory systems?

A
  • Location
  • Capacity
  • Unit of Transfer
  • Access Method
  • Performance
  • Physical Type
  • Physical characteristics

Includes aspects such as volatile/nonvolatile and erasable/nonerasable.

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2
Q

What is the main memory?

A

The memory used to store programs and data during computer operation, primarily using semiconductor integrated circuits.

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3
Q

What types of chips are used in main memory?

A
  • RAM
  • ROM

RAM chips can be static or dynamic.

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4
Q

What is the function of the bootstrap loader?

A

To start the computer software when the power is turned on.

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5
Q

What is cache memory?

A

A special very high-speed memory used to speed up data access for the CPU by holding frequently requested data and instructions.

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6
Q

Define temporal locality.

A

The tendency of the time intervals between references to a given address to be small.

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7
Q

Define spatial locality.

A

The tendency of the distances between consecutive memory references to be small.

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8
Q

What is a cache hit?

A

When the processor finds the memory location in the cache.

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9
Q

What is a cache miss?

A

When the processor does not find the memory location in the cache.

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10
Q

What is hit ratio in cache memory?

A

Hit ratio = hits / (hits + misses) = Number of hits / Total accesses.

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11
Q

What is miss penalty?

A

The time to move a block from a lower level in the hierarchy to satisfy the processor’s request.

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12
Q

What are the levels of cache memory?

A
  • Level 1: Registers
  • Level 2: Cache memory
  • Level 3: Main Memory
  • Level 4: Secondary Memory
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13
Q

What is the purpose of cache mapping?

A

To specify the correspondence between main memory blocks and those in the cache.

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14
Q

What is direct mapping in cache memory?

A

Maps each block of main memory into only one possible cache line.

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15
Q

What is the formula for determining the cache line in direct mapping?

A

Line number = j mod number of cache lines.

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16
Q

How many bits are required to determine the byte within a cache line if the line length is 32 bytes?

A

5 bits.

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17
Q

What is the total number of cache lines if the cache size is 64K and the line size is 32 bytes?

A

2048 lines.

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18
Q

In a direct mapped cache, how is the tag size calculated?

A

Tag size = Number of bits in physical address - (Number of bits in line number + Number of bits in block offset).

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19
Q

What is the tag directory size formula?

A

Tag directory size = Number of lines in cache x Number of bits in tag.

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20
Q

What is set associative mapping?

A

Cache lines are grouped into sets, where each set contains k number of lines, allowing a memory block to map to any available line within its set.

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21
Q

What is the cache set number formula in set associative mapping?

A

Cache set number = Main Memory Block Address Modulo Number of sets in Cache.

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22
Q

What is the formula to determine the cache set number a main memory block maps to?

A

(Main Memory Block Address) Modulo (Number of sets in Cache)

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23
Q

In set associative mapping, how many cache lines can a particular block of main memory map to?

A

One particular cache set only

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24
Q

What is required if the cache is full?

A

A replacement algorithm

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25
Q

What is the total number of words in a cache consisting of 128 blocks of 16 words each?

A

2048 words

26
Q

How many bits are there in the physical address for a main memory of size 128 KB?

A

17 bits

27
Q

What is the number of bits in the block offset for a block size of 256 bytes?

A

8 bits

28
Q

How do you calculate the total number of lines in cache?

A

Cache size / Line size

29
Q

What is the number of sets in a cache if there are 64 lines and a set size of 2?

A

32 sets

30
Q

How many bits are in the tag if the physical address is 17 bits, and there are 5 bits in the set number and 8 bits in the block offset?

A

4 bits

31
Q

What is the size of the tag directory if there are 64 lines in cache and each tag is 4 bits?

A

32 bytes

32
Q

What are the three types of cache memory mapping?

A
  • Fully associative
  • Direct-mapped
  • N-way set associative
33
Q

What is the advantage of fully associative mapping?

A

More flexible than direct mapping

34
Q

What is the hit ratio if there are 3 hits and 20 total requests?

A

3/20

35
Q

In a direct-mapped cache, what happens when a new block arrives for a line that is already occupied?

A

The existing block is replaced

36
Q

What is the hit ratio for a fully associative cache using LRU policy if there are 5 hits and 17 total requests?

A

5/17

37
Q

How many blocks are in a fully associative cache with a size of 512 KB and a block size of 1 KB?

A

512 blocks

38
Q

What is the size of the main memory if the physical address is 27 bits?

A

128 MB

39
Q

In FIFO cache replacement, what is the hit ratio for 15 memory references with 5 hits?

A

1/3

40
Q

What is the hit ratio for 2-way set associative mapping if there are 5 hits out of 15 references?

A

1/3

41
Q

What is the total number of hits in the cache replacement scenario?

A

5

This is based on the initial memory references given.

42
Q

What is the hit ratio calculated from the total hits and memory references?

A

5 / 15

The hit ratio is the number of hits divided by the total number of memory references.

43
Q

What is the number of hits using the LRU cache replacement algorithm?

A

6

This is calculated from the memory references processed using the LRU algorithm.

44
Q

What is the hit ratio using the LRU cache replacement algorithm?

A

6 / 15

Reflects the number of hits over the total memory references.

45
Q

What is the number of hits using the Direct Mapping cache replacement algorithm?

A

6

This is derived from the same set of memory references.

46
Q

What is the hit ratio using the Direct Mapping cache replacement algorithm?

A

6 / 15

The ratio remains the same as the LRU algorithm for this set of references.

47
Q

What is the cache memory block formula?

A

Block j of MM % Number of Cache Blocks

This formula is used to determine which cache block a memory address maps to.

48
Q

What is the number of hits using the 2-way set associative mapping with LRU?

A

5

This is the count of hits when using a 2-way set associative mapping strategy.

49
Q

What is the hit ratio using the 2-way set associative mapping with LRU?

A

5 / 15

This ratio is consistent with the number of hits calculated.

50
Q

For the given memory reference 5, what is the result in the Direct Mapping algorithm?

A

miss

The memory reference results in a miss as per the calculations.

51
Q

For the given memory reference 12, what is the result in the Direct Mapping algorithm?

A

miss

The first occurrence of 12 results in a miss.

52
Q

For the given memory reference 13, what is the result in the Direct Mapping algorithm?

A

miss

The first occurrence of 13 results in a miss.

53
Q

For the given memory reference 17, what is the result in the Direct Mapping algorithm?

A

miss

The first occurrence of 17 results in a miss.

54
Q

For the given memory reference 4, what is the result in the Direct Mapping algorithm?

A

miss

The first occurrence of 4 results in a miss.

55
Q

For the given memory reference 12, what is the result in the LRU algorithm?

A

hit

The second occurrence of 12 results in a hit.

56
Q

For the given memory reference 13, what is the result in the LRU algorithm?

A

hit

The second occurrence of 13 results in a hit.

57
Q

For the given memory reference 19, what is the result in the LRU algorithm?

A

miss

The first occurrence of 19 results in a miss.

58
Q

For the given memory reference 43, what is the result in the LRU algorithm?

A

miss

The first occurrence of 43 results in a miss.

59
Q

For the given memory reference 61, what is the result in the LRU algorithm?

A

miss

The first occurrence of 61 results in a miss.

60
Q

For the given memory reference 19 in the Direct Mapping algorithm, what is the result?

A

miss

The first occurrence of 19 results in a miss.

CAO (6 decks)

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