Module 2

Question 1

In the V-Model, In the Verification Phase, Low Level Design(LLD), is validated how?

Answer 1

Component Testing

Question 2

In the V-Model, In the Verification Phase, High Level Design(HLD), is validated how?

Answer 2

System Integration Testing

Question 3

Whats two new diagram types from SysML, that UML does not utilize?

Answer 3

Parametric Diagram and Requirement Diagram

Question 4

Whats four different diagrams that are the same as UML 2, in SysML diagram?

Answer 4

Sequence, State Machine, Use Case and Package Diagram1

Question 5

Whats the three different diagrams modified from UML 2, in a SysML a diagram?

Answer 5

Activity, Block Definition and Internal Block

Question 6

Whats the four kinds of diagrams in SysML?

Answer 6

Structure, Behaviour, Requirements and Parametrics