Module 1

Question 1

Computer Architecture

Answer 1

Concerned with the structure and behavior of computer systems as seen by the user,includes information, formats , instruction sets and techniques for addressing memory(describes what a computer does)

Question 2

Fuctional units of a computer

Answer 2

computer system is divided into 5 separate units for its operation:

Input Unit
Output Unit
ALU
Control Unit
Memory

Question 3

Input and output unit

Answer 3

input unit reads data from a source and translates it to ADC for transfer into the CPU

whereas the Output unit converts DAC into human readable form ,sends processed results to the outside world

Question 4

Memory Unit

Answer 4

Collection of storage cells with associated circuits needed to transfer data in and out of the storage

Computer stores in different methods which leads to different levels in storage
primary and secondary

Question 5

ALU

Answer 5

This unit performs the actual processing of data and instructions

Question 6

Control Unit

Answer 6

this unit determines the sequence in which computer programs and instructions are to be executed

Operations of input output and alu are co ordinated by this unit
data transfers are also done by this unit

Question 7

CPUt

Answer 7

ALU CU and MU of a computer system are jointly know as the CPU its also know as the brain of the computer system

Question 8

Basic operational concepts

Answer 8

to perform a given task appropriate program consisting of a list of instructions stored in the memory and these instructions can be loaded from the meory into the processor for its execution

Load - transfers data to register
Store - transfers data to memory
Add
Sub
etc

Question 9

Basic operational concepts(Operating steps)

Answer 9

1 Program resides in memory
2Execution starts when PC points to the first
instruction in the program
3 MAR reads the control signal
4 memory loads address word into MDR
5 Contents are transfered to IR
6 IR decodes and executes the instructions (gets operands for ALU)
7 performs the operation in ALU and stores the result back into GPR
8 transfers result into memory
9 during the execution pc is incremented

Question 10

MAR

Answer 10

holds the address of the location to be accessed

Question 11

Bus structures

Answer 11

its a pathway for digital signals to rapidly move data
consists of 3 set of lines used to carry address data control signals
together these 3 make up the system bus,which is a internal bus intended to connect the processor with internal h/w devices

Question 12

Data bus

Answer 12

typically 8,16,32 or 64 bit
the width reflects the mx amount of data that can be tranfered at a time
a 64 bit procsessor has a 64 bit data bus
bi directional bus

Question 13

Computer architecture Vs Organization

Answer 13

1)
CA CO order
deals with what the computer does

how the computer does it

2)
Deals with high leve design issues
Deals with low level design issues

3)
Functional behaviour
Structural relationship

4)
Desgining computer first

designing computer second

aka architecure before archi

5)
involves instruction set , addy mode , data types

invloves circuit design,signals,ALU and memory

Question 14

Primary memory Vs secondary memory

Answer 14

1)
Refers to main memory

refers to auxilary/secondary/external memory

2)
Holds the data or instruction that are currently in use

Used to store and retrive data or info on a long term basis

3)
Nature of primary memory varies from volatile and non

non volatile in nature

4)
data is directly accessed by CPU

data isnt directly accessed by the CPU

5)
more expenseive

less expensive

Question 15

Load R2,LOC

Answer 15

this instruction reads the content of a memopry location represented by LOC is loaded into the processor register R2

orginal contents of LOC are preserved

Question 16

ADD R2,R5 ,R1

Answer 16

Adds the contents of R1 and R5 and places thier sum into register R4
contents in R2 and R5 remain unchanged but contents in R1 are changed

Question 17

Store R4,LOC

Answer 17

coptes the operand in R4 to memory location LOC

Question 18

Contents of processor

Answer 18

PC-Holds/points to the address of the next executing instruction IR-Holds the instruction that is being currently executed, MAR MDR CU ALU and GPRs R0 to Rn-1- they serve a varity of functions

Question 19

Interrupt

Answer 19

Normal execution of a program may be halted or preempted if some device requires urgent servicing

In order to deal with the situation the normal execution of the program will be stoped to handle the interrupt signal

Provides a meoth to postponme or delay the current process perform a sub routine and then restart the standard program again

uses ISR

ISR-saves the internal state of the processor in mmemory before the serviceing of the interrupt began

Question 20

Address bus

Answer 20

the physical location of the data in memory is carried by the address bus

the address bus carries only the information regarding the address and is synchronzed with the data bus to accomplish read/write tasks from the processor

if there are n address bus the size of the memoy will be 2^n

address bus is always unidirectional

Question 21

Control bus

Answer 21

the control bus carries control info from the control units to other units

the controlling information is used for directing the activities of all units

whether the data is read or written is determined by the control bus

2 important control signals are READ ad WRITE

Question 22

Types of bus structures

Answer 22

Single bus and multi bus

1)
allows only one transfer at a time

allows two or more transfers at a time

2)
cost is low

cost is high

3)
low performance

high performance

4) flexible for attaching peripheral devices

provides concurrency in operation

Question 23

Memory location

Answer 23

the memory consistts of many millions of storage cells each of which can store a bit of data having values 0 or 1 the memory is organized so that a a group of n bits can be stored or retrived in a single basic operation
memory of a compouter can be schematically represented as a collection of words

Question 24

Word

Answer 24

group of n bits where n is the word length

mordern computers have word length of 16 to 64

if the word length of a computer is 32 bit signed number of four ASCII encoded charecters each occuppy 8 bits

Question 25

Memory address

Answer 25

accessing the memory to store or retrive a single item of information either a word or a byte requires distinct names or addresses for each location its customary to use numbers from 0 to 2^k - 1 for some suitable value of K thus the memory can have upto 2^k addressable locations

Question 26

Big Endian and little endian assignments

Answer 26

There are 2 ways thatm byte address can be assigned accross words the name big endian is used when lower bytes addressses are used for the more significant bytes of the word(leftmost) the name little endian is used where the lower byte addresses are used for the less significant bytes of the word (rightmost) both are used in commerical machies

Question 27

Memory Operation

Answer 27

2 basic operations READ transfers a copy of a the contents of a specific memor location to the processor the memory contents remain unchanged to start the read the process the address of the dsired location and request for its cotents to be read Write transfers an item of info from the process to a specific memory location overwriting the former contents of that location

Question 28

register transfer noations

Answer 28

the transfer of info from one location in the computer to another possible locations are memory locations processor registers or registers in the I/O sub system right hand side of RTN denotes a value and left hand side holds the location eg: R2-> r1 +r3 loc<- R2

Question 29

[LoC]

Answer 29

contents on Loc(brackets denote conents of the location Loc)

Question 30

Assembly language notation

Answer 30

notation to represent machine instructions and programs example: Load R2, Loc Load dest,source Add R1,R2,R3 in the above examples we used dthe english words load and add to denote the required operations

Question 31

Differnt types of instructions

Answer 31

at the start of execution of a program all instruictions and data used in the program are stored in the memory of the computer Store source,dest load dest,source 'Add dest,source,source

Question 32

instruction execution

Answer 32

executing a given instruction is a 2 phase procedure in the first phase called instruction fetrch the instruction is fetched from the memory location whose address is in the PC this instruction is then placed in IR in the processor at the start of the next phase called instruction execute the instruction is examed to determine which instruction is to be performed and what operands are used and then the specified opeartion is executed by the processor

Question 33

Branching

Answer 33

its a type of instruction taht a loads a new address into the pc as a resuslts the processor fetches and executes the instruction

Question 34

Types of addressing mode

Answer 34

# indicates that its a immediate value 1 Register mode- the operand is the content of a processor register, name of the register is given in the instruction eg:clear r1 move r1,r2 2 Absolute/direct mode - the operand is in memory location , the address of this location is given explicity in the instruction eg: Mov Loc,R2 3 Immediate mode The operand is given explicityly in them instruction 4 Indirect mode- The effective address is the conent of a register ' () - indicates the indirect mode similar to a pointer eg:Add (R1),Ro Index mode the effective address of teh operand is generated by adding a constatnt value to the contents of a regiwster EA = X + [r] Relative mpde the effiective address is determine by the index mode using the pc in place of GPR the relative mode basicaly represents as X(PC) -> x->[PC] auto increment and decrement mode the effictive address of the operand is the contents of a register specified instruction after accessing the operand the contents of the regiters are automatically incremented to point to the next item in a last (R)+ increment 1 for 8 bits 2 for 16 etc after accessing the operand the contents of the regiters are automatically decremented and then used as effective address of the operand \ in a last -(R)

Question 34

Register transfer Logic

Answer 34

to describe a digital system in terms of functions such as adder decoder and registers a mehtod called register transfer is used in this registers are selected as primitive components of the system

Question 35

Compoentns of digital system

Answer 35

set of registers in the system and thier functons the binary coded info stored in the register operation performed on the info stored on the register the control functions that initiate the sequence of operations

Question 36

Micro operations

Answer 36

operation performed on the data stored in registers are called micro opertaions the result of operation may replace the previous binary information of a register

Question 37

Types of micro operations

Answer 37

Inter register transfer - it doesnt change the content when binary info moves from one register to another Arithemethic operations - it performs arithemetic operation on numbers stored on register Logical operation - performs logical AND OR operataions on indiviual pairs of bits Shift operations - specify operations for shift registers

Question 38

Types of registers

Answer 38

R1/A process regster(8 bit) MAR PC IR status

Question 39

SHift operations

Answer 39

used for serial transfer of data 3 types of shift arithemetic - keeps the MSB the same even after shift for right shift for left its normal shift circular - CIL and CIR logical - SHL and SHR

Question 40

Processor Unit

Answer 40

part of digital computer that implements the operations in the system includes no of registers and digital functios that implement AL shift and transfer microoperations

Question 41

CPU

Answer 41

processor unoit combined with control unit that supervises the sequnce of micro operation all computer implements operations by a sequence of micro operations processoer part of cpu is referred as data path of cpu bcz the operation forms that path for data transfers b/w registers in the unit paths are controlled by means of gate

Question 42

Processor organization

Answer 42

different methods of organizing processor unit are bus organization registers in PU are connected thru common buses and arranged as a small memory unit each register is connected to two multiplexeeers to form bus a nd b (mux selects input registers) selection lines of the multiples selects one register for bus a and b function selected by alu operation is performed shift microoperations are peformed by the shifter (transfer of ALU to bus S) result goes thru the output bust s into the input of all the registers the destination register that recives info from output bus is selected by decoder ScrathPad memory the register in pu can be enclosed in a small location called scratchpad memory cheaper -less wires single register in a group is slected by giving addy to memory unit Source is selected by specifiying the corresponding word address and activating the memory read its manipulated in alu and shifter the reult of the operation is transfered to the memory register by specifiying address and activating memory write 2 port memory 3 seperate addy lines to select 2 words of memory simultaneously 2 source registers are read at the same time if destination register is same source register then the micro operation can be done i one clock when enabled me the destination will be set as b the clock input controls the memory read and write thru WE Accumulator its a sepearte register in some processor unit for addition abbrivation is A or AC first number is added to 0 and sum is transfered to AC secondn umber is added with number in accumulator and newly formed sum replaces the previous accumulator value

Question 43

ALU (design)

Answer 43

its a digital circuit that performs arithemetic and logic operations has a number of select lines to select a partifcular operation in the unit selections are decoded within the alu meaning k lines can serve 2^k distince operations mode select i/p operation choose b/w logical and arithemetic operations (0 arithermetic and 1 logical) 2 function selects s1 and s0 secify the operation to be generated Arithemetic Unit basic section of arithemetic section of an ALU is parallel adder pareallel adder is constructed with number of full adder circuits connected in cascade by controlling the inputs to the parallel adder we can obtain different types of arithemetic operations opearation in parallel adder F=A+B f=A+B+1 add with carry F=A+B' a plus 1's comp of b F=A+B'+1 Subtraction F=A+0+0 transfer A F=A+0+1 increment A F=A+ all 1's +0 = A-1 = decrement A F=A+ all 1's +1 = transfer A Logic circuit since all logic operations can be made using and nor and not since we employ 2 selection lines we can select 4 operations so we also used XOR function for the logic design ALU the logic circuit can be combine with arithemetic circuit to produce one ALU

Question 44

Status register

Answer 44

its a hardware regiuster that contains information about the state of the processor its some time convenient to supplement the ALU with a status register wheere these status bit conditions are stored for further analysis status bits are someitmes called flag bits or conditional codes the four status bits are symbolized by ZVCS The bits are set on cleared as a result of an operation performed in ALU

Question 45

Multiplication of unsigned numbers

Answer 45

the product of 2 unsigned n digit numbers can be accommodated in 2 n digits

Question 46

Array multipleer

Answer 46

binary multiplication of unsigned operands can be implemented in a combinational two dimensonal logic array the main componenet of each cell in a FA the and gaete i each cell determines whether multiplicant mj is added to the incoming partial product bit based on the value of the multipleier bit Qi

Question 47

Booths algo rithm

Answer 47

generates a 2n-bit product and treats both + ve and -ve 2's compliment n bit operands uniformaly Steps Multiplicant is placed in M and Multiplier in Q register A is set to 0 Q-1 is also set to = count = n number of bits compare Q and Q1 if 00 and 11 no operation 01 A+M 10 A-M ASHR

Question 48

Data

Answer 48

discrete elements of information that are manipulated by microoperation

Question 49

Logic desgin

Answer 49

process for deriving the digital circuits that perform data processing and the digital circuits tat provide control signals

Question 50

One flipl flop per state method

Answer 50

uses one flip flop per state in the control sequenctial circuit only one ff is active at a time other are cleared one bit propagates from one ff to another under the control of decision logic uses maximum no of FFs one for each state advantages simplicity saves desin effory operational simplicity disadvantage high system cost since more FFs are used method is also called ring counter controller

Question 51

Sequnce Register and decoder method

Answer 51

Uses a register to sequnce the control states register is decoded to provide one o/p for each state

Question 52

PLA control

Answer 52

the external sequnce register establishes the present state of the control circuit the PLA outputs determine which micro operations should be initiated depending on the external input conditions and the present state of the sequnce register at the same time pla determies next state of sequence register

Question 53

Micro program control

Answer 53

the control variable cna be represented by a string of 1's and 0's called control word the control words can be programmed to inititate the various componenets in the system in an organized manner a control unit whose control variable are stroeg in a memry is called a micro programmed control unit each word of memory is called mincroinstruction sequnce of micro instructions is called micro program

Question 54

Accessing of I/O devices

Answer 54

Some addresses in the addresss space of the processor are assigned to the i o locations rather than to the main memory these locations are usually implemented as bit storage circuits oragnized in the form of registers refered to as i/o registers since the i/o device and memory share the same address space this arrangement is called memory mapped I/O with memory mapped i/o any manchine instruction that can access memory can be used to transfer data from or to i/o devices

Question 55

I/O device interface

Answer 55

an i/o device is connected to the interconnection network by using a circuit called device interface which provides the means for data transfer and for the exchange of status and control info needed to facilitate the data transfers and govern the operation of the device ineterface includes some registers that can be accessed by the processor to , serve as a buffer for data transfers hold info about the current status of the device

Question 56

programmed controlled I/O

Answer 56

various methods to access and operate these devices are polling method the processsor repeatdly checs a status flag to achive the required synchronization b/w processor and i/o device Interrupt method= synch is achived by hanging i/o device send over a singal ver the bus when its ready for data transfer DMA- direct memory addy - technique for high speed I/p device here the device interface transfer data directly to or from the memory without continous involvement by the processor

Question 57

ISR

Answer 57

routine executed in respone to an interrupt request assume that an interrupt arrive duing the execution of instruction i the processor first comples execution of i then it loads the pc with the address of hte first ISR ttherfore when interrupt happens current contents of pc must be kept in a temp storageinter

Question 58

Interrupt acknowledgement

Answer 58

a special control signal sent by the processor to inform the device that its interrupt signal has been recognized and that it may remove its interrupt req signal

Question 59

Interrupt latency

Answer 59

the delay b/w the time an interrupt is recived and start of ISR

Question 59

vectored interrupts

Answer 59

allocates permanently in an area in the memory to hold the addresses of ISRs

Question 59

enabling and disabling interrupts

Answer 59

the processor has a status register (ps which contains infpoo about its current state of operation and it contains a bit called IE which deals with disabling interru;pts

Question 59

Interrupt nesting

Answer 59

organized in priority structure

Question 59

Procedure of interrupt handling

Answer 59

the device raises a interrupt request the processor intrupts the program currently being executed and saves the contetens of PC and PS registers interrupts are disabled by clearing IE bit in the ps to 0 the action req bny the interrupt is performed by the ISR and during which the device is informed that its req has been recognized and in response it deactivates the interrupt request signal Upon completion of the ISR the saved contents of the PC annd PS registers are restored and execution of interrupted program is resumed

Question 59

handling multiple devices

Answer 59

based on interrupt priority

Question 59

Pipelining

Answer 59

Pipelining is a technique used in computer architecture to improve the performance of a processor by increasing the number of instructions that can be executed in a given time. It is a “logical pipeline” that allows the processor to perform an instruction in multiple stages, rather than completing one instruction before moving on to the next. How Pipelining Works The pipelining process can be broken down into several stages: Fetch: The processor retrieves an instruction from memory. Decode: The instruction is decoded and the necessary information is extracted. Execute: The instruction is executed. Writeback: The results of the instruction are written back to memory or registers.

Question 60

DMA

Answer 60

DMA Controller is a type of control unit that works as an interface for the data bus and the I/O Devices. As mentioned, DMA Controller has the work of transferring the data without the intervention of the processors, processors can control the data transfer. DMA Controller also contains an address unit, which generates the address and selects an I/O device for the transfer of data. Here we are showing the block diagram of the DMA Controller.

Question 61

Hardwired control

Answer 61

can be assumed as a sequenctial digital system design as per the contents of IR the external I/ps and states are selected the outputs are the control signals hardwired design of control system assumes the design of data flow as per the wiring of the components the design of the hardwired control is carried out in 5 steps: 1:statement of the problem : addition and subtraction of 2 fixed point binary nuymbers represented in sign magnitude form the addition fo 2 numbers stored in registors of finite length may result in a sum that exceeds the storage capacity of the register by one bit the extra bit is said to cause an overflow FFs are used to store the overflow bit 2: initial equipment config is assumed As and Bs registers to store the sign bit E for overflow B and A register to store its magnitude ALU Control Logic