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Mod 4 > Mod 4 > Flashcards

Mod 4 Flashcards

1
Q

Binary digit 1 or 0

A

Bit

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2
Q

Grouping of eight digits

A

Byte

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3
Q

Grouping of 16 digits

A

Word

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4
Q

The left-most bit represents a positive or negative number

A

Sign bit

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5
Q

Represents text Data American Standard code for information interchange and is 7 bits

A

ASCII

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6
Q

All eight bits to represent 256

A

Extended ASCII

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7
Q

16 bit character encoding system capable of representing the alphabets and symbols of all the world’s languages

A

Unicode

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8
Q

Continuous signal with the potential for an infinite amount of signal resolution

A

Analog signal

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9
Q

Sequence of discrete values

A

Digital signal

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10
Q

Reduces file size without losing quality

A

Lossless compression

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11
Q

Reduces file size but loses some quality

A

Lossy compression

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12
Q

Letters that follow the . of a filename

A

File extension

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13
Q

Normally the first few bytes within a file and has nothing to do with the files name

A

File signature

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14
Q

Scientific notion for very large or small numbers

A

Order of magnitude

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15
Q

Use of electronic switches to solve Boolean functions and is fundamental to how computers are built and handle data

A

Digital logic

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16
Q

Electronic device that performs a Boolean operation

A

Logic gate

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17
Q

Interfaces with the processor memory and one or more peripheral devices

A

I/O table

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18
Q

Expression composed of Boolean variables and connectives

A

Boolean expression

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19
Q

A collection of logic gates configured to perform a particular function

A

Digital circuit

20
Q

Allows instructions and data to be stored in memory rather than being manually entered

A

Stored program concept

21
Q

Small amounts of storage space used to perform operations two types, GPR and SPR

A

Registers

22
Q

The vocab of commands understood by the CPU and is therefore an interface that allows all software to run on Hardware

A

Instruction set architecture ISA

23
Q

A short character sequence, this represents instructions for LMC to execute

A

Mnemonics

24
Q

Machine code that numonics map directly to the first digit in LMC instructions, represents the operation to be performed

A

Opcode

25
Q

The last two digits in LMC instructions represents the object to be manipulated

A

Operand

26
Q

Instruction cycle for the LMC

A

Fetch decode execute F-D-E

27
Q

The stored program concept is made up of what three components

A

CPU memory and I/O

28
Q

What are the LMC registers

A 
Accumulator GPR 
program counter spr 
instruction register spr 
memory address spr 
memory data spr
29
Q

What is the LMC’S GPR

A

Accumulator

30
Q

List the LMC’s SPR’s

A

Program counter
instruction register
memory address
memory data

31
Q

What is the mnemonic for opcode 5

A

Load or LDA

32
Q

What is the mnemonic for opcode 9

A

Input or INP

33
Q

This is a complex instruction set computer

A

CISC

34
Q

Computer architecture using one instruction for one operation

A

RISC

35
Q

This is a memory to register architecture

A

X86

36
Q

RISC based processor that runs smartphones and tablets

A

Advanced RISC machine

37
Q

This is stored in memory by most significant byte first

A

Big Endian

38
Q

This is stored in memory by least significant byte first

A

Little endian

39
Q

this is when any task done by software can be done by Hardware in any operation performed directly by Hardware can be done using software

A

Principle of equivalence

40
Q

This is used by ARM each instruction contains three operands they waste space but are faster and result in good performance

A

Fixed-length instruction

41
Q

These are some instructions within the ISA and are different sizes

A

Variable length instruction

42
Q

Hardwired software programs on top of hard wire to implement the ISA

A

Microprogrammed

43
Q

X86 architecture that supports data processing operations on both the register and memory

A

Memory to register

44
Q

Used by RISC architecture that supports data processing operations performed in registers and never directly in memory

A

Load / store

45
Q

Implementation technique that allows overlapping execution of multiple instructions in a single fetch decode execute (F-D-E) datapath

A

Pipe lining

46
Q

Uses a single fetch decode data path leading to multiple ALU’S allowing for more than one instruction per clock cycle

A

Sperscalar processor

Mod 4 (1 decks)

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