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Mod 4 #2 > Mod 4 #2 > Flashcards

Mod 4 #2 Flashcards

1
Q

the overall computer system performance, enhanced by a single Improvement is limited by the amount the improved feature is used

A

Amdahl’s law

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2
Q

One operation performed on many pieces of data

A

Short Vector processing

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3
Q

The classification of computer architectures based on instructions and data

A

Flynn’s taxonomy

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4
Q

Two or more processors on a single chip allowing multiple instructions to execute simultaneously

A

Multi-core processing

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5
Q

Increases utilization of a single processor by transferring instructions from multiple threads

A

Multi-threaded processing

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6
Q

Computer systems using multiple processors

A

Multiprocessor systems

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7
Q

Special-purpose processor for graphics also good for Math and encryption

A

Graphics Processing Unit GPU

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8
Q

Integrated circuit configured by the customer using software known as Hardware description language

A

Field programmable gate arrays

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9
Q

What are five segments of memory where programs are loaded

A 
Stack 
freespace 
Heap 
bss 
data
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10
Q

What are two ways to implement the control unit

A

Hardwired and microprogrammed

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11
Q

What CU implementation method does the x86 use

A

Microprogrammed implement the ISA

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12
Q

Which computer architecture uses fixed-length instructions

A

Risc

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13
Q

Which computer architecture uses variable-length instructions

A

Cisc

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14
Q

Which Benchmark for measuring computer systems is favored by computer manufacturers

A

Standard performance evaluation Corporation spec

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15
Q

Which multiprocessor system communicates through memory

A

Symmetric shared memory

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16
Q

Which multiprocessor system communicates through an interconnection

A

Asymmetric multi-processing or distributed shared memory

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17
Q

What bus line is used for interrupts in synchronization

A

Control line

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18
Q

What is the difference between a multi point and point to point bus

A

Multi-point connect more than two components connects only two components

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19
Q

What component is used to connect unlike buses

A

Bridge

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20
Q

What protocol uses asynchronous Communications

A

Serial communication

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21
Q

Which is maskable interrupts or exceptions

A

Both

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22
Q

What is the difference between an interrupt in an exception

A

Interrupt indicates Hardware needs serviced

exception is the byproduct of an error while executing an instruction

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23
Q

What term is used to describe an interrupt or an exception that must be dealt with immediately

A

Non maskable

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24
Q

What vectors of the x86 IDT are non maskable interrupts and exceptions

A

0 through 31

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25
Q

How does the control unit keep the status of a processor when servicing an interrupt

A

It saves variables and registers to memory

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26
Q

What buses are attached to the North Bridge

A

Memory and digital video

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27
Q

What buses are attached to the South Bridge

A 
PCI 
USB 
SCSI 
IDE 
SATA  
audio
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28
Q

Which I/O interface category provides serial Communications

A

Serial

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29
Q

Name two I/O interfaces used for video

A

Video graphics array VGA

digital video interface DVI

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30
Q

What are the memory hierarchy levels from fastest to slowest access time

A 
Registers      bit
cache      byte
primary      RAM
secondary      magnet disc
external.
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31
Q

Which of the three cache a methods of replacement requires a history or frequency of used blocks

A

Least recently used lru

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32
Q

Which of the two cache mapping schemas require searching to find the correct block

A

Associative

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33
Q

Updates the Block in main memory when the cash block becomes a victim block

A

Wright back

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34
Q

Independent cache for data and instructions one or the other but not both

A

Harvard cache

35
Q

A virtual address is known as what

A

A page

36
Q

A physical address is known as what

A

A frame

37
Q

Random access memory RAM allows for reading and writing data what are the two types

A

Static Ram sram

Dynamic Ram dram

38
Q

Made of D flip flop circuits that hold data as long as there is power e.g. cache memory

A

Static Ram

39
Q

Made of little batteries that leaked electricity called capacitors the most common main memory solution is double data rate a type of synchronous dram that returns double the data

A

Dynamic Ram

40
Q

Read-only memory ROM is non-volatile and consist of what

A

Programmable ROM
erasable programmable ROM EPROM
ELECTRICALLY ERASABLE PROGRAMMABLE ROM EEPROM

41
Q

The sector portion of a platter traditionally holds how many bytes of data

A

512

42
Q

Disk performance is measured by what

A 
Spin up time 
seek time 
rotational latency 
transfer time 
disk access time
43
Q

What RAID level is generally used for file servers

A

Raid 5

44
Q

Connects the internal components of a computer and moves data back and forth

A

Bus

45
Q

Form and method that computer components use to transmit data between the sender and receiver

A

Bus protocol

46
Q

Allows for communication between dissimilar buses

A

Bridge

47
Q

Physical means for the peripheral devices to interface with the computer also referred to as ports

A

Device interface

48
Q

Processor memory and bus on the same ship

A

SOC system on a chip

49
Q

series of steps to coordinate a synchronous Communication in which the sender and receiver proceed to The Next Step only when both parties agree that the current step was completed

A

Hand shaking

50
Q

The act of temporarily storing data in a region of physical memory called a buffer

A

Buffering

51
Q

system for resolving bus control conflicts and assigning priorities to bus control request in a multi-point bus topology where there is more than one Master

A

Bus arbitration

52
Q

A synchronous event typically triggered by an IO device

A

Interrupt

53
Q

Synchronous event resulting from the execution of an instruction that disrupts program execution

A

Exception

54
Q

time it takes memory to Output set data once the memory controller receives a data request its measured in bus clock Cycles before main memory returns data

A

Latency

55
Q

Rate at which data is loaded from in stored to memory memory bandwidth measures and bits per second

A

Throughput

56
Q

What type of memory is memory that can be lost

A

Volatile memory

57
Q

When the needed data is in the cache

A

Cache hit

58
Q

When a block in cache is selected for replacement

A

Victim block

59
Q

Instead of transferring only the data needed this transfers the entire block of data

A

Locality principle

60
Q

A concentric circle on the platter

A

Track

61
Q

A combination of tracks across all platters

A

Cylinder

62
Q

Made of flash memory in common replacement for disks built on arrays of nand or nor memory circuits

A

Solid state drive SSD

63
Q

Can an IO module have more than one device in their face

A

Yes

64
Q

Is the CPU connected to the same bus as memory

A

No

65
Q

What component is needed to connect the memory bus and the io bus

A

Bridge

66
Q

Which of the two communication categories uses sequential groups of bits via multiple data lines and also uses synchronous communication

A

Parallel Communications

67
Q

which of the three types of bus arbitrations connect devices in a series with Device closest to the Arbiter getting control of the bus

A

Daisy chain

68
Q

Which of the three types of bus arbitration uses priorities which are assigned to each device on the bus

A

Distributed using self-selection

69
Q

Which of the four IO control methods requires more overhead of the processor

A

Programmed IO

70
Q

What are the three classes of exceptions

A

Faults traps aborts

71
Q

What is an example of a non maskable exception

A

Division error

72
Q

Which of the four IO control methods requires each IO device to have an allocated segment of memory

A

Memory mapped

73
Q

What is the last step performed by the device to terminate dma

A

Acknowledge notify the processor of completion

74
Q

What is an example of a bus that uses asynchronous Communications

A

SATA

75
Q

Where is the cache physically located within the computer

A

CPU

76
Q

What two attributes does the tlb map

A

Page and frame

77
Q

From which of the three types of ROM is flash memory created

A

EEPROM

78
Q

General purpose register used for any purpose stores data or address is for the programmer

A

GPR general purpose register

79
Q

These are special purpose registers for One Singular purpose

A

Segment register

80
Q

Holds info about the most recently performed ALU operation memory alignment endianness and disabling of interrupt and sets processor operating mode

A

Status and control registers

81
Q

Dictates which instructions in architectural features are available

A

Moods of operation

82
Q

Ensure security of the system through process isolation

A

Privilege levels

83
Q

Most frequently used instructions data is moved from register to register in register to memory

A

Data movement instruction

Mod 4 #2 (1 decks)

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