Mod 4 #2 Flashcards
the overall computer system performance, enhanced by a single Improvement is limited by the amount the improved feature is used
Amdahl’s law
One operation performed on many pieces of data
Short Vector processing
The classification of computer architectures based on instructions and data
Flynn’s taxonomy
Two or more processors on a single chip allowing multiple instructions to execute simultaneously
Multi-core processing
Increases utilization of a single processor by transferring instructions from multiple threads
Multi-threaded processing
Computer systems using multiple processors
Multiprocessor systems
Special-purpose processor for graphics also good for Math and encryption
Graphics Processing Unit GPU
Integrated circuit configured by the customer using software known as Hardware description language
Field programmable gate arrays
What are five segments of memory where programs are loaded
Stack freespace Heap bss data
What are two ways to implement the control unit
Hardwired and microprogrammed
What CU implementation method does the x86 use
Microprogrammed implement the ISA
Which computer architecture uses fixed-length instructions
Risc
Which computer architecture uses variable-length instructions
Cisc
Which Benchmark for measuring computer systems is favored by computer manufacturers
Standard performance evaluation Corporation spec
Which multiprocessor system communicates through memory
Symmetric shared memory
Which multiprocessor system communicates through an interconnection
Asymmetric multi-processing or distributed shared memory
What bus line is used for interrupts in synchronization
Control line
What is the difference between a multi point and point to point bus
Multi-point connect more than two components connects only two components
What component is used to connect unlike buses
Bridge
What protocol uses asynchronous Communications
Serial communication
Which is maskable interrupts or exceptions
Both
What is the difference between an interrupt in an exception
Interrupt indicates Hardware needs serviced
exception is the byproduct of an error while executing an instruction
What term is used to describe an interrupt or an exception that must be dealt with immediately
Non maskable
What vectors of the x86 IDT are non maskable interrupts and exceptions
0 through 31
How does the control unit keep the status of a processor when servicing an interrupt
It saves variables and registers to memory
What buses are attached to the North Bridge
Memory and digital video
What buses are attached to the South Bridge
PCI USB SCSI IDE SATA audio
Which I/O interface category provides serial Communications
Serial
Name two I/O interfaces used for video
Video graphics array VGA
digital video interface DVI
What are the memory hierarchy levels from fastest to slowest access time
Registers bit cache byte primary RAM secondary magnet disc external.
Which of the three cache a methods of replacement requires a history or frequency of used blocks
Least recently used lru
Which of the two cache mapping schemas require searching to find the correct block
Associative
Updates the Block in main memory when the cash block becomes a victim block
Wright back
Independent cache for data and instructions one or the other but not both
Harvard cache
A virtual address is known as what
A page
A physical address is known as what
A frame
Random access memory RAM allows for reading and writing data what are the two types
Static Ram sram
Dynamic Ram dram
Made of D flip flop circuits that hold data as long as there is power e.g. cache memory
Static Ram
Made of little batteries that leaked electricity called capacitors the most common main memory solution is double data rate a type of synchronous dram that returns double the data
Dynamic Ram
Read-only memory ROM is non-volatile and consist of what
Programmable ROM
erasable programmable ROM EPROM
ELECTRICALLY ERASABLE PROGRAMMABLE ROM EEPROM
The sector portion of a platter traditionally holds how many bytes of data
512
Disk performance is measured by what
Spin up time seek time rotational latency transfer time disk access time
What RAID level is generally used for file servers
Raid 5
Connects the internal components of a computer and moves data back and forth
Bus
Form and method that computer components use to transmit data between the sender and receiver
Bus protocol
Allows for communication between dissimilar buses
Bridge
Physical means for the peripheral devices to interface with the computer also referred to as ports
Device interface
Processor memory and bus on the same ship
SOC system on a chip
series of steps to coordinate a synchronous Communication in which the sender and receiver proceed to The Next Step only when both parties agree that the current step was completed
Hand shaking
The act of temporarily storing data in a region of physical memory called a buffer
Buffering
system for resolving bus control conflicts and assigning priorities to bus control request in a multi-point bus topology where there is more than one Master
Bus arbitration
A synchronous event typically triggered by an IO device
Interrupt
Synchronous event resulting from the execution of an instruction that disrupts program execution
Exception
time it takes memory to Output set data once the memory controller receives a data request its measured in bus clock Cycles before main memory returns data
Latency
Rate at which data is loaded from in stored to memory memory bandwidth measures and bits per second
Throughput
What type of memory is memory that can be lost
Volatile memory
When the needed data is in the cache
Cache hit
When a block in cache is selected for replacement
Victim block
Instead of transferring only the data needed this transfers the entire block of data
Locality principle
A concentric circle on the platter
Track
A combination of tracks across all platters
Cylinder
Made of flash memory in common replacement for disks built on arrays of nand or nor memory circuits
Solid state drive SSD
Can an IO module have more than one device in their face
Yes
Is the CPU connected to the same bus as memory
No
What component is needed to connect the memory bus and the io bus
Bridge
Which of the two communication categories uses sequential groups of bits via multiple data lines and also uses synchronous communication
Parallel Communications
which of the three types of bus arbitrations connect devices in a series with Device closest to the Arbiter getting control of the bus
Daisy chain
Which of the three types of bus arbitration uses priorities which are assigned to each device on the bus
Distributed using self-selection
Which of the four IO control methods requires more overhead of the processor
Programmed IO
What are the three classes of exceptions
Faults traps aborts
What is an example of a non maskable exception
Division error
Which of the four IO control methods requires each IO device to have an allocated segment of memory
Memory mapped
What is the last step performed by the device to terminate dma
Acknowledge notify the processor of completion
What is an example of a bus that uses asynchronous Communications
SATA
Where is the cache physically located within the computer
CPU
What two attributes does the tlb map
Page and frame
From which of the three types of ROM is flash memory created
EEPROM
General purpose register used for any purpose stores data or address is for the programmer
GPR general purpose register
These are special purpose registers for One Singular purpose
Segment register
Holds info about the most recently performed ALU operation memory alignment endianness and disabling of interrupt and sets processor operating mode
Status and control registers
Dictates which instructions in architectural features are available
Moods of operation
Ensure security of the system through process isolation
Privilege levels
Most frequently used instructions data is moved from register to register in register to memory
Data movement instruction
