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Computer System Fundamentals > Midterm > Flashcards

Midterm Flashcards

1
Q

How do you objectively campare the complexity of two circuits

A

number of gates. max propogation delay, number of transistors

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2
Q

JSR - 6502

A

jump to sub routine, push the address of the next op on to the stack

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3
Q

TSX - 6502

A

transfer stack pointer to x.

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4
Q

minumum # of basic logic gates for a half adder

A

2

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5
Q

minimmum # of basic logic gates for a full adder

A

5

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6
Q

Universal set

A

express any boolean function using only the gates in S

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7
Q

Name the universal sets

A

AND,OR,NOT NAND NOR AND, NOT

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8
Q

SCRAM lacked circuitry for what commands?

A

JMZ, ADD, SUB

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9
Q

the ones complement of signed integers has two zeros +0 and -0

A

true: 0000, 1111

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10
Q

Ones compliment

A

obtained by inverting all bits in the binary number. negative if first digit is 1

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11
Q

6502 BNE command

A

branches if zero flag is clear.

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12
Q

6502 BCC

A

branches if carry flag clear

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13
Q

6502 BCS

A

branches if carry flag set

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14
Q

6502 BEQ

A

branches if zero flag set

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15
Q

6502 BMI

A

branch if negative flag set

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16
Q

6502 BPL

A

Branches if negativ eflag clear

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17
Q

6502 BVC

A

branch if overflow flag clear

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18
Q

6502 BVS

A

branch if overflow flag set

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19
Q

twos compliment of 5 bit range

A

-2^4 to 2^4 -1

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20
Q

The encoding for all 6502 instructions is between 2 and 4 bytre long

A

false, sta $ffff is 5 bytes, ASL and TXA are 1

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21
Q

of SCRAM machine instructions

A

16 - there are 16 pins

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22
Q

6502 CLC

A

clear carry flag

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23
Q

6502 CLD

A

clear decimal mode flag

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24
Q

6502 CLI

A

clear interrupt disable flag

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25
Q

6502 CLV

A

clear overflow flag

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26
Q

6502 SEC

A

set carry flag

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27
Q

6502 SED

A

set decimal mode flag

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28
Q

6502 SEI

A

set interrupt disable flag

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29
Q

6502 ASL

A

arithmetic shift left

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30
Q

6502 LSR

A

logical shift right

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31
Q

6502 ROL

A

rotate left

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32
Q

6502 ROR

A

rotate right

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33
Q

CPX, CPY, CMP 6502

A

compare x, compare y, compare accumulator

\The compare instructions subtract (without carry) an immediate value or the contents of a memory location from the addressed register, but do not save the result in the register. The only indications of the results are the states of the three status flags: Negative (N), Zero (Z), and Carry (C). The combination of these three flags indicate whether the register contents are less than, equal to (the same as), or greater than the operand “data” (the immediate value or contents of the addressed memory location. The table below summarizes the result indicators for the compare instructions.

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34
Q

ADC/SBC 6502

A

Add/sub with carry

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35
Q

6502 PHA. PHP, PLA, PLP

A

Push accumulator on stack Push processor status on stack pull accumulator from stack pull processor status from stack

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36
Q

LDA, LDX, LDY

A

Load accumulator, load x, load y

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37
Q

add $a, $b, $c

A

a = b + c

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38
Q

addu $a, $b, $c

A

add unsigned

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39
Q

addi

A

adds constant

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40
Q

lw $t, C($s)

A

load word from MEM[$s + c] and following 3 bytes

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41
Q

lb $t, C($s)

A

loads byte from MEM[$s + c]

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42
Q

sw $t, C($s)

A

stores word into MEM[$s + c] and next 3 bits

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43
Q

sb $t, C($s)

A

stores the least-significant 8 bits of a register into MEM[$s +c]

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44
Q

and $d, $s, $t

A

bitwise $d = $s & $t

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45
Q

andi $t, $s, C

A

pads leftmost 16 bits with -s

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46
Q

beq $s,$t,C

A

jumps to c if equal

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47
Q

bne $s,$t,C

A

jumps if not equal

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48
Q

j C

A

jump to C

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49
Q

jr $s

A

go to address $s

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50
Q

jal

A

calls subrotine, jumps and links by copying program counter to $ra

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51
Q

MIPS add to stack

A

sub $sp, 4 sw $ra, ($sp)

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52
Q

MIPS subtract from stack

A

lw $ra, 0($sp) add $sp, 4 jr $ra

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53
Q

twos complement range

A

-2^(N-1) to 2^(N-1) - 1

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54
Q

twos complement

A

invert digits and add 1

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55
Q

NAND - and gate

A
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56
Q

NAND - OR gate

A
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57
Q

NAND - NOT Gate

A
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58
Q

NOR - AND gate

A
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59
Q

NOR - or gate

A
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60
Q

NOT From NOR gate

A
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61
Q

xor

A
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62
Q

RS latch

A
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63
Q

shift register

A
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64
Q

DNF

A

disjunctive normal form - zeros

a’b’ + ab

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65
Q

CNF

A
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66
Q

half adder

A
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67
Q

full adder

A
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68
Q

D type RS Latch

A
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69
Q

edge triggered, master slave flip flop

A
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70
Q

Bits of memeory in SCRAM

A

16 8 bit memory slots = 128bits

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71
Q

Size of addresses for SCRAM

A

4 bit

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72
Q

OP Code size in SCRAM

A

4 bits

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73
Q

total SCRAM instruction size

A

op code + addr = 8 bit

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74
Q

sign and magnitude

A

first bit says +/-

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75
Q

5 steps to pipelining MPS

A
  1. Fetch Instruction - read from memory
  2. Instruction Decoding - read source registers
  3. Execution- execute
  4. Memory Access - read/write
  5. Write Back- store
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76
Q

JMZ

A

jump in 6502 if AC is 0

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77
Q

issue with JMZ

A

no connection from IR to PC

no way to tell if AC was 0

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78
Q

Edge-triggered D-type flip-flop

A
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79
Q

6502 interrupt

A

IRQ does the following:

The CPU has a input labelled IRQ
When the pin is pulled low/ has 0 applied to it - a signal is sent to the CPU.
The CPU halts the current program and runs the Interrupt Service Routine.

This specifically works by:

finishing the current instruction
pushing the PC to the stack (addr of the next instruction)
Interrupt disable flag is set
a 16 bit address is read from $FFFE-$FFFF and put into PC
That is where the ISR lives and needs to be supplied.

The interrupt service routine must retrieve a copy of the saved status register from where it was pushed onto the stack and check the status of the B flag in order to distinguish between an IRQ and a BRK.

80
Q

Distincy boolean functions of n arguments

A

2^(2^n)

81
Q

D-Type Master-Slave Edge-triggered flip flop description

A

D-Type Master-Slave Edge-triggered flip flop:
Data is captured on rising edge and output changes state on falling edge
of the clock. First D-latch is master, second D-latch is slave and gets inverted
Clock input.When clock signal changes from 0 to 1, output of slave latch takes
value of output of master latch, since by the time the slave is open, the master
already has taken the input, and can’t receive any more.

82
Q

CNF

A

ANDS of Ors

83
Q
A
84
Q

DNF

A

OR of ANDS

85
Q

AB + CD DNF OR CNF

A

DNF

86
Q

(A+B)(C+D)

A

Conjunctive Normal Form

87
Q

RS LATCH circuit with nands

A
88
Q

RS LATCH NOR Truth table

A
89
Q

RS LATCH with NORS circuit

A
90
Q

RS Latch Nand truth table

A
91
Q

RS LATCH NAND - Invalid state

A

S=0 R=0

92
Q

LATCHED STATE NAND RS LATCH

A

R,S both = 1

93
Q

Avoid invalid state on RS latch

A

this not gate makes the inputs always compliments of eachother

94
Q

D Latch

A

Transparent latch

When enabled - whatever D is - Q is.

When disabled it stores the last value

95
Q
A
96
Q

Edge Trigger

A
97
Q

D flip flop

A

D type latch with an enable that is connected to a clock and an edge trigger

98
Q

How a D-type master slave edge triggered flip flop works

A

Data is captured on rising edge and output changes state on falling edge
of the clock. First D-latch is master, second D-latch is slave and gets inverted
Clock input.When clock signal changes from 0 to 1, output of slave latch takes
value of output of master latch, since by the time the slave is open, the master
already has taken the input, and can’t receive any more.

99
Q

CAFE in binary

CAFE in decimal

CAFE in base 8

A

Binary: 1100 1010 1111 1110

Decimal: 5 1966

Octal: 14 5376

100
Q

abs can be done without branches

A

true

101
Q

describe pipeline proces`

A

1) fetch instruction IF = instruction fetch; assembler has turned pseudo instruction into actual cpu instruction
2) instruction decoding ID, understanding what instruction it is, what resources it needs, read some of the registers if needed
- - only load and store access memory
3) execution, EX drop to ALU, etc
4) if instruction needs to access memory, memory access stage MEM
5) write back, take what instruction computed and store it in the right register WB

102
Q

structural hazard

A

structural hazard: run out of hardware, e.g. can’t do two additions at the same time. not a problem with mips. hardware

103
Q

data hazards

A

occur when the pipeline changes the order of read/write accesses to operands so that the order differs from the order seen by sequentially executing instructions on the unpipelined machine.

104
Q

Saving registers on interrupts.

A

The interrupts essentially jump to to the ISR (interrupt service routine). This ISR can do anything - and the main program will have no idea. So, it is responsible for saving the registers so that the program can continue.

Example situation - the keyboard is connected to IRQ and causes an interrupt whenever it is clicked to avoid polling. Say that the keyboard needs to use registers to store info about what keys are pressed. In this case - we do not want registers to be trashed and it is the calee’s responsibility to handle this - so we preserve the registers.

In fact, the interrupts cannot save to the stack to the best of my knowledge because the interrupt could be called due to a corrupted stack pointer. Therefore, the memory is preserved in statically allocated chunk of global memory.

105
Q

two examples of data hazards.

A

Example:
(1) - add $t0, $t1, $t2
(2) - add $t7, $t0, $t8
Instruction (2) needs value from (1). WB is when the result is
available but at this point (2) is already at MEM, which is an issue
because that means it used the old value at $t0.

Can be avoided by forwarding:
Result of $t0 is already available at EX stage. We can add a path
for output of EX back into EX, which allows updated $t0 to be available
for (2).

Example:
(1) - lw $t0, 16($t7)
(2) - add $t1, $t0, $t9
Both instructions depend on $t0. (1) result is only available at MEM
stage after (1) loaded from memory, so (2) can’t execute. Can’t do anything
about it, so you’re forced to stall and do nothhing in EX for one cycle

106
Q

What architechture is MIPS

A

RICS - reduced instruction set computing

107
Q

CISC

A

Complex Instruction Set Computing

108
Q

6502 Specs

A
  • 8 bit accumulator. 3
  • 8 bit registers.
  • X,Y,P.
  • 16 bit addresses.
  • Memory: 64kb
109
Q

Absolute Adressing 6502

A

An instruction has explicit address in memory

Prefeced with $.

110
Q

Absolute with X/Y Adressing

A

Access what is in the specified memory location + contents of X/Y

$ffff, x or ,y

111
Q

Zero PAge Adressing 6502

A

memory in first 256 bytes of memory where msb is 0. Does one lestt memory fetch during execution.

112
Q

relative adressing 6502

A

*+4, gives you an offset

113
Q

indirect adressing 6502

A

JMP ($40,x) load byte indirectly from memory.

114
Q

Indexed Indirect Addressing (only works with X)

A

Ultimately gives an array of pointers indexed by X.

If X = 1, and LDA ($11, X) is called, then 1 is added to 11 (which gives
12) and we look at the addresses 12 and 13 together. If address 12
contained FE and address 13 contained CA, then we would then look at
the contents of memory address CAFE.

115
Q

Indirect Indexed Addressing (only works with Y)

A

With Y = 1, assume LDA ($10, Y) is called. We then look at the addresses
10 an 11 together. If address 10 contained 00 and address 11 contained C0,
then we would then look at the contents of memory address C000 + Y, which
is C001.

116
Q

6502 endedness

A

6502 is littleendian which means right most bytes is the op code. Instruction is left most. Adress is stored in reverse order.

117
Q

MIPS specs

A

32 registers. 32 bits each. 4gb of memory.

118
Q

3 addre

A
119
Q

$zero

A

always zero register

120
Q

$at

A

asembler temporary

121
Q

$v*

A

function results

122
Q

$a*

A

function arguments

123
Q

$t*

A

temporaries

124
Q

$s*

A

saved temporaries

125
Q

$sp

A

stack pointer

126
Q

$ra

A

return address

127
Q
A
128
Q

Write through

A

update cache and ram. Bring into cache and RAM concurrently

129
Q

Write Buffer

A

Queue of pending writes so you dont need to wait for RAM to finish, just add to buffer. Best for few writes among many reads.

130
Q

Write Back

A

Only update cache. When you load other things after there are more misses -write it back once you miss. Requires a dirty bit, write back on eviction from cache

131
Q

Write allocate

A

read block from memory then write. Painful if want to initialize all to 0, tons of reads tat we dont need to do. If there are lots of writes but almost n oreads.

132
Q

No write allocate

A

just write to memory, not going to read at all. JUST write to RAM. Wait for read - only fill cache when there is a reade.

133
Q

SCRAM memory width

A

8 bits

134
Q

SCRAM adress size. Instruction size

A

4 bits each

135
Q

PC SCRAM

A

program counter. 4 bit register that holds current address

136
Q

Accumulator SCRAM

A

8 bit register

137
Q

CLU SCRAM

A

centeral logic unit, has all pins. controls flow.

138
Q

MAR SCRAM

A

memory address register, Feeds into memory block

139
Q

MBR Scram

A

memory address buffer- takes data from memory

140
Q

SCRAM IR

A

holds op code and addr. Instruction Register.

141
Q

6502 Endidness

A

Little Endian

142
Q

Accumulator size 6502

A

8 bit

143
Q

3 Registers 6502

A

A register (arithmatic)

X register - index register only inc/dec

Y register - same as X

P register - status register, holds all flags.

ALL 8 Bits

144
Q

6502 memory size

A

64kb, 6 bit addr space 2^16 bytes.

145
Q

6502 Compares

A

CMP, CMX, CMY setzero and carry flags

146
Q

6502 branch instructions

A

if statements to jump

BCC, BCS, BEQ, BNE

147
Q

6502 increament/decrements instructions

A

incx, incy.

148
Q

6502 shift/rotates

A

ASL,LSR

ROR,ROL

149
Q

6502 Jump Instructions

A

JMP - go to addr in memory

JSR - jump to subroutine

RTS - return from subroutine

150
Q

Stack instructions 6502

A

PHP,PHA,TSX,TSX, PHA,PHP

151
Q

6502 Absolute Addressing

A

Supplying instruction w/numberical addr:

LDA $FE

152
Q

6502 absolute x/y addressing

A

XY offsets access memory +x or y

STA $0200,X

153
Q

6502 Immediate Addressing

A

uses the value not the value at the address

and #$1f

154
Q

6502 zero page addressign

A

adresses that are only 8 bits 00-FF faster access

155
Q

6502 indexed indirect addressing

A

works only with x register

does address + x then loads two adjacent addresses

156
Q

6502 indirect indexed addressing

A

gets two adresses adjacent. adds Y to that address.

157
Q
A
158
Q

MIPS internal improvements

A

higher clock speeds, pipelining

159
Q

MIPS architechture bit

A

32

160
Q

MIPS memory size

A

4GB

161
Q

MIPS # registers/size of each

A

32 registers, 32-bits each

162
Q

jump MIPS

A

j

163
Q

How to do ifs with MIPS

A

slt - set if less than

slt $t0, $t1, $t2 t2=1 or 0

branch seperate.

164
Q

MIPS at

A

asssembler temporary

165
Q

MIPS v0,v1

A

output/return values

166
Q

MIPS a0-a3

A

inputs/parameters

167
Q

MIPS t0-t7

A

temporaries

168
Q

MIPS s0-s7

A

saved registers

169
Q

MIPS sp

A

stack pointer

170
Q

MIPS ra

A

return address

171
Q

dynamic branch prediction simple

A

either taken or not taken gueses. Flaw: first last guess in loop will be wrong

172
Q

dynamic branch prediction complex

A

taken, not taken

taken maybe, not taken maybe

if taken or taken maybe it will be taken again

173
Q

memory heirarchy

A

register

internal cache

2 level cahce

tetriery cahce

physical memory

disk

174
Q

block/line cache

A

min amount of info/memory in the cache or that can be brought into the cache

175
Q

hit rate

A

fraction of memory accessess found in cche

176
Q

miss rate

A

1 - hit rate

177
Q

hit time

A

access time fro cache

178
Q

miss penalty

A

time to get from RAM

179
Q

direct mapping

A

one slot fo each tag

180
Q

set associative

A

>1 slot for each tag

181
Q

Random evicion policies

A

good bottom line for comparison (not hardware)

182
Q

FIFO

A

first in first out. throw out whats been there the longest. can implement in hardware.

183
Q

LRU eviction policiess

A

least recently used. takes care of problem that FIFO could forget loop conter. Throws out what you have used the least often.

184
Q

size of slot

A

log2(#sets)

185
Q

size of offset

A

log2(block size)

186
Q

tag

A

32 - slot - offset

187
Q

x86 size of registers/number

A

8 32 bit registers

188
Q

ESP

A

stck pointer

189
Q

EBP

A

base pointer

190
Q

size of addresses x86

A

32

191
Q

[ebx] vs ebx

A

[ebx] address held in ebx so moving into [ebx] moves into the address held at ebx

192
Q

x86 push

A

pushes stack by decrementing ESP by 4. Places operand into 32 bit location at ESP.

193
Q

x86 Pop

A

removess 4 byte data from top of hardware stack. Moves 4 bytes into sp then into specified register. Increaments esp by 4.

194
Q
A
195
Q

6502 instruction size

A

1-3 bits

196
Q

6502 address size

A

16

197
Q
A

Computer System Fundamentals (1 decks)

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