Brainscape's Knowledge GenomeTM

Browse over 1 million classes created by top students, professors, publishers, and experts.


See full index

Embedded Systems > Midterm 1 > Flashcards

Midterm 1 Flashcards

1
Q

Embedded System

A

A special computer designed for specific control functions

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
2
Q

Components of an embedded system

A
  1. Sensor (input)
  2. Controllers (logic + calculation)
  3. Actuator (physical output)
How well did you know this?
1
Not at all
2
3
4
5
Perfectly
3
Q

Cyber-physical system

A

Embedded system + physical environment

Note: Physical considerations should impact the way we think about logic

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
4
Q

Embedded controllers in order of efficiency

A
  1. ASIC
  2. FPGA
  3. DSP
  4. MPU
How well did you know this?
1
Not at all
2
3
4
5
Perfectly
5
Q

Embedded controllers in order of flexibility

A
  1. MPU
  2. DSP
  3. FPGA
  4. ASIC
How well did you know this?
1
Not at all
2
3
4
5
Perfectly
6
Q

Behavior of a GPIO pin is determined by ________ at ________

A

the user

at run time

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
7
Q

“Previously” on a UML Activity Diagram indicates…

A

We need a STATE VARIABLE to keep track of the previous state

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
8
Q

What controller does the Atmel SAM Xplained Pro use?

A

ARM Cortex M4 MPU

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
9
Q

Inputs must be configured with…

A
  1. An internal pull-up resistor (default is HIGH)

2. An internal pull-down resistor (default is LOW)

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
10
Q

What replaces macros with their definitions?

A

The compiler

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
11
Q

ASIC- about

A
  • Application Specific IC
  • Does ONE task only
  • Gates/transistors are physically on the IC
  • Not reprogrammable

Ex. Satellites

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
12
Q

ASIC- pros

A
  1. Most efficient
  2. Fast
  3. Best performance
How well did you know this?
1
Not at all
2
3
4
5
Perfectly
13
Q

ASIC- cons

A
  1. Design is challenging and slow
  2. Expensive
  3. Not reprogrammable
How well did you know this?
1
Not at all
2
3
4
5
Perfectly
14
Q

FPGA- about

A

-Field Programmable Gate Array

Ex. FPGA + I2C at NI

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
15
Q

FPGA- pros

A
  1. Fast
  2. Power efficient
  3. Programmable
How well did you know this?
1
Not at all
2
3
4
5
Perfectly
16
Q

FPGA- cons

A
  1. Big

2. Harder to reprogram than a microprocessor

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
17
Q

DSP- about

A
  • A specialized microcontroller
  • uses software
  • PARALLELISM to increase efficiency
How well did you know this?
1
Not at all
2
3
4
5
Perfectly
18
Q

DSP- pros

A
  1. Efficient

2. Programmable

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
19
Q

Microprocessor- about

A
  • a GENERAL PURPOSE processing unit
  • runs software

Ex. BeagleBone, desktop computer, Atmel boards, phones, etc.

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
20
Q

Microprocessor- pros

A
  • flexible

- cheap

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
21
Q

Microprocessor- cons

A

Least efficient

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
22
Q

Types of microprocessors

A
  1. MPU
  2. CPU
  3. DSP
  4. System on a Chip (SoC)
  5. System in a package (SiP)
How well did you know this?
1
Not at all
2
3
4
5
Perfectly
23
Q

MPU

A
  • a STANDALONE CPU

- 32 or 64 bits

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
24
Q

MCU (microcontroller)- about

A
  • a single-chip machine with a processor AND peripherals
  • built-in peripherals (RAM, ROM, TC, IO Ports)
  • usually no OS

Ex. Atmel board

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
25
Q

MCU- pros

A
  1. Low power
  2. Simple
  3. Cheap
How well did you know this?
1
Not at all
2
3
4
5
Perfectly
26
Q

DSP Chip- about

A
  1. A single chip with a DSP + peripherals for signal processing (ex. Fast RAM)
  2. Parallel processing/pipelining
How well did you know this?
1
Not at all
2
3
4
5
Perfectly
27
Q

DSP chip- pros

A
  1. Fast (low latency)

2. Better quality ADC/DAC

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
28
Q

SoC- about

A
  1. Advanced processing device with ALL PERIPHERALS ON ONE CHIP
  2. Usually has an OS

Ex. Smartphones

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
29
Q

SiP- about

A

Like SoC
BUT puts components on multiple dies and puts them into a SINGLE PACKAGE
for modularity

Ex. BeagleBone Black

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
30
Q

ARM

A

Advanced RISC Machines

RISC- complex actions compiled by several simple instructions

Low energy, low cost

32 DATA registers (NOT memory registers)

Pipelining

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
31
Q

NVIC priority levels

A

8 to 256

We have 16

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
32
Q

Why do we need pull-up/pull-down resistors?

A

Without them, GPIO pins are left “floating”

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
33
Q

DMA

A

Direct Memory Access

Allows USART to access memory directly
Copies printf statement to RAM where USART will send out data

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
34
Q

Peripheral DMA Controller

A

Allows microprocessor to access peripherals (ex. USARTx) by writing to and reading from the memory addresses (even though they are separate devices)

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
35
Q

Interrupt (definition)

A

A signal to the processor emitted by hardware or software indicating a event that needs immediate action

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
36
Q

Types of interrupts

A
  1. External- ex. Button press, serial message received
  2. Internal- ex. SysTick, processor fault
  3. Exception- ex. Divide by zero
How well did you know this?
1
Not at all
2
3
4
5
Perfectly
37
Q

Interrupt handling: when a processor detects an interrupt, it…

A
  1. Halts normal execution
  2. Saves the current program state
  3. Calls the interrupt handler
How well did you know this?
1
Not at all
2
3
4
5
Perfectly
38
Q

Interrupt Handler Code is usually written by ________

A

The user to perform a needed task

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
39
Q

Interrupt Handler code executes until…

A

Completion

Then return to the previous program execution

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
40
Q

Interrupt interface to the processor is required for

A
  1. Internal interrupts- interrupts from the processor (ex. Fault, clock timer)
  2. External interrupts- interrupts from devices external to the processor (ex. GPIO pins)
How well did you know this?
1
Not at all
2
3
4
5
Perfectly
41
Q

What does the NVIC do?

A
  1. Reads all internal and external interrupt requests (IRQ’s)
  2. Evaluates interrupts in order of priority
  3. Calls the interrupt Handler with the highest priority IRQ
How well did you know this?
1
Not at all
2
3
4
5
Perfectly
42
Q

Interrupt masking

A

Allows software to ignore specific interruptions

Set via binary values where each bit represents a particular interrupt

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
43
Q

Most embedded systems are…

A

Real-time Systems

Need a clock to keep track of deadlines

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
44
Q

ARM Cortex M4 system timer

A

Built in with SysTick

24-but timer

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
45
Q

SysTick_Handler

A

Automatically reloads SYST_CVR With SYST_RVR when SYST_CVR = 0

46
Q

Calculate the elapsed time for SysTick

A

Elapsed time = NumTicks*(time/tick)

47
Q

Event Driven systems

A

Use interrupts (instead of edge-triggered polling) to execute time-sensitive instructions

Process

  1. Event is detected
  2. NVIC evaluates the priority
  3. If the interrupt has the highest priority, it is executed in the callback function
  4. Otherwise, the interrupt is put into a vector and is executed when it has the highest priority
48
Q

Vectored Interrupts

A

Context: two interrupts are called such that the execution of their events overlap, and Interrupt 1 has a higher priority that Interrupt 2

  1. When Interrupt 2 occurs, it’s IRQn is placed in the NVIC Vector in priority order
  2. When Interrupt 1 finishes, the IQRn in the vector with the highest priority executes
49
Q

Nested Interrupts

A

Context: two interrupts are called such that the execution of their events overlap, and Interrupt 2 has a higher priority that Interrupt 1

  1. When Interrupt 2 occurs, the NVIC interrupts the Interrupt 1 Handler and executes the Interrupt 2 Handler
  2. When Interrupt 2 finishes, the NVIC will resume execution of Interrupt 1
50
Q

About Callbacks

A
  1. AUTOMATICALLY called when an event occurs
  2. Must be set up during initialization
  3. It is NEVER explicitly called; this means that the cows doesn’t need to be “watching” for a condition
51
Q

Interrupt Sources

A
  1. SysTick Timer (internal)
  2. EIC (parameters set by user, fancy)
  3. GPIO (external, MUST have GPIO Driver Mod; triggered ANY TIME the GPIO pin changes levels)
52
Q

What allows the processor to distinguish between Interrupts?

A

The IQRn

53
Q

External Device Interface

A

External Device Interface =
Communication protocol +
Interface Design

54
Q

Communication protocol is typically defined by __________

A

A standard

Ex. USB, I2C (TWIM), SPI, UART

55
Q

Interface Design is typically defined by ________

A

The sensor’s data sheet or an ICD (interface control doc.)

Describes the info that needs to be sent/received

56
Q

Communication Protocols

A
  1. UART
  2. SPI
  3. I2C, TWIM
57
Q

UART- about

A

Universal ASYNCHRONOUS Receiver/Transmitter

  1. A common serial port (Putty)
  2. Connects devices that are on the same OR different devices
  3. EITHER device can transmit data at ANY TIME
  4. NO COMMON CLOCK- use settings (baud rate, start/stop bits, parity, etc. to synchronize)
58
Q

UART- pros

A
  1. Asynchronous nature (not always practical to synchronize)

2. Can transmit and receive AT THE SAME TIME (separate Rx and Tx lines) controlled by flow control

59
Q

UART- cons

A
  1. Start/stop bits add overhead and decrease efficiency
  2. Complex circuitry
  3. Clocks that vary slightly distort data
60
Q

SPI- about

A

Serial Peripheral Interface

  1. Connects peripherals ON THE SAME DEVICE
  2. SYNCHRONOUS (because peripherals are on the same clock)
  3. Master/Slave System (usually microprocessor is the master and it produces a clock signal)
  4. Short distance comm. for 1 device
61
Q

SPI- pros

A
  1. Synchronous

2. Simple circuitry

62
Q

SPI- cons

A

Requires a connection for every slave

a lot of hardware

63
Q

Baud Rate

A

(Speed)
Clock rate for the sender AND receiver
Data sampled on the rising/falling clock edge

64
Q

I2C / TWIM- about

A
  1. Allows multiple “slave” digital IC’s to communicate with one or more masters
  2. Short distance comm. for 1 device
  3. 2 signal wires to exchange info: SCL (generated by master) + SDA
  4. Open drive: can only pull signals LOW and has a pull up resistor to restore signal to HIGH
65
Q

I2C / TWIM- pros

A

Best of UART and SPI

  1. Overcomes asynchronous-related probs
  2. Fewer connections than SPI, but no bus contention like UART
66
Q

I2C / TWIM- cons

A

Some overhead (ACK/NACK per 8 bits)

67
Q

Stop bits

A

The number of bits required to indicate that transmission has stopped

Note: Data bits are those between the Start and Stop bits

68
Q

Parity

A

Simplest form of error detection

Parity = sum(data bits) + parity

69
Q

Flow control

A

Allows the receiver to request that the sender temporarily stop sending data when buffers are getting full

70
Q

T/F Soft deadlines can run on a standard OS

A

True

71
Q

T/F Hard deadlines can run on a standard OS

A

False

72
Q

Why can we execute hard deadlines on the Atmel board?

A

We’re not running anything else

73
Q

Period tasks

A

Tasks must be updated every p periods of time

Ex. Reading and updating the temperature

74
Q

Aperiodic (Sporadic) Tasks

A

Tasks request the processor at unpredictable times

Handled with Interrupts
Ex. Button press

75
Q

Preemptive Task

A

External events that interrupt running tasks

Result: unpredictable execution times (jeopardizes real-time deadlines)

76
Q

Non-preemptive Tasks

A

Tasks are executed until completions

Interrupts must wait for current running task to finish

Result: external events may need to wait a long time before running

77
Q

Static Schedulers

A
  1. Makes decisions at DESIGN TIME
  2. Implements decisions at compile time
  3. Like pulling
  4. Entirely Time Triggered (TT)
78
Q

Dynamic Schedulers

A
  1. Make decisions at RUN TIME
  2. Flexible
  3. Unaware of resource requirement or dependencies
  4. Result: non-deterministic behavior
79
Q

Types of aperiodic scheduling without precedence constraints

A
  1. Earliest Due Deadlines (EDD)
  2. Earliest Deadline First (EDF)
  3. Least Laxity (LL)
80
Q

EDD- about

A

Static scheduler

Executes tasks in order of non-decreasing deadlines

Goal: minimize latensss

81
Q

EDD- requirements

A

All tasks are

  1. Independent
  2. Known ahead of time (because it’s a static scheduler)
  3. Ready to execute
82
Q

Earliest Deadline First (EDF)

A

Dynamic scheduler with preemption

Like EDD, but accounts for varying arrival times

Queues tasks and sorts them by Deadline

83
Q

Least Laxity- about

A

Dynamic scheduler with preemption

Laxity = Deadline - (current time + duration remaining)

84
Q

Least Laxity- requirements

A

Knowledge of execution times

85
Q

Precedence

A

When tasks depend on other tasks

86
Q

Aperiodic scheduling with precedence constraints

A

Latest Deadline First (LDF)

87
Q

Latest Deadline First (LDF)

A

Aperiodic
No scheduling constraints
Non-preemptive
Optimal for single processor systems

Puts tasks in a queue based on

  1. No successors
  2. Latest Deadline

Reverse queue to get execution order

88
Q

Periodic utilization

A

U = sum(ci / pi)

89
Q

Rate Monotonic Scheduling

A

RMS
Periodic scheduler
Fixed priorities (shortest period has highest priority)

90
Q

RMS Assumptions

A
  1. all tasks that have hard deadlines are periodic
  2. All tasks are independent
  3. di = pi for all tasks
  4. ci is constant and known for all tasks
  5. Time required for context switching is negligible
91
Q

RMS Inequality

A

u = sum(ci / pi) <= n(2^1/n -1)

GUARANTEES SCHEDULABILITY

92
Q

RMS utilization u for large n

A

lim = n*(2^1/n - 1) = 0.7

93
Q

Earliest Deadline First (EDF)

A

Dynamic priorities that change at runtime based on which task has the earliest Deadline

94
Q

RMS- how are priorities determined?

A

Shortest period has highest priority

95
Q

What do timer counters do?

A

Count down from a particular register value and generate an interrupt when the register value reaches zero

Ex. SysTick

96
Q

SAM4L Timer Counters

A

There are 2 with
3 channels that work independently

Connected to a peripheral bus clock

97
Q

T/F: microprocessor often have a built-in GPIO module

A

False

Microprocessors are standalone processors

98
Q

T/F: The RAM for a microcontroller is part of the microcontroller chip

A

True

Micro-controllers have the works

99
Q

T/F: if you do not configure an input to use an internal pull-up resistor, that input will read 0 every time it is read

A

FALSE

Not configuring the input leaves in “floating” so it yields inconsistent results

100
Q

How does the processor communicate printf’s to the USART module

A

DMA

101
Q

Will the processor finish executing configure_console when an interrupt is called?

A

No

The processor will immediately go to the interrupt Handler

102
Q

Max SysTick Reload Value Register (SYST_RVR):

A

2^24

Because SysTick is a 24-but register

103
Q

How do you determine the value for SYST_RVR

A

(Processor freq.)*(time elapsed)

104
Q

What calls interrupt handlers?

A

The NVIC

105
Q

T/F: EIC Interrupts can be used be used on any GPIO on the SAM4LC4C microcontroller

A

FALSE

EIC Interrupts can only be used on pins that are physically to the EIC module

106
Q

To communicate with an external device, you must….

A

Combine knowledge about:

Communication Protocol + Interface Design

107
Q

T/F: I2C and SPI are both synchronous

A

TRUE

108
Q

Synchronous means…

A

Sharing a common clock

109
Q

SPI Wires

A 
SCK (clock)
MOSI (master out slave in)
MISO (mastic in slave out)
SS1
SS2
.
.
.
SSn
110
Q

T/F: In I2C, the master must initiate every transmission

A

TRUE

Embedded Systems (1 decks)

Brainscape helps you reach your goals faster, through stronger study habits.
© 2024 Bold Learning Solutions. Terms and Conditions