Midterm 1 Flashcards
(110 cards)
1
Q
Embedded System
A
A special computer designed for specific control functions
2
Q
Components of an embedded system
A
- Sensor (input)
- Controllers (logic + calculation)
- Actuator (physical output)
3
Q
Cyber-physical system
A
Embedded system + physical environment
Note: Physical considerations should impact the way we think about logic
4
Q
Embedded controllers in order of efficiency
A
- ASIC
- FPGA
- DSP
- MPU
5
Q
Embedded controllers in order of flexibility
A
- MPU
- DSP
- FPGA
- ASIC
6
Q
Behavior of a GPIO pin is determined by ________ at ________
A
the user
at run time
7
Q
“Previously” on a UML Activity Diagram indicates…
A
We need a STATE VARIABLE to keep track of the previous state
8
Q
What controller does the Atmel SAM Xplained Pro use?
A
ARM Cortex M4 MPU
9
Q
Inputs must be configured with…
A
- An internal pull-up resistor (default is HIGH)
2. An internal pull-down resistor (default is LOW)
10
Q
What replaces macros with their definitions?
A
The compiler
11
Q
ASIC- about
A
- Application Specific IC
- Does ONE task only
- Gates/transistors are physically on the IC
- Not reprogrammable
Ex. Satellites
12
Q
ASIC- pros
A
- Most efficient
- Fast
- Best performance
13
Q
ASIC- cons
A
- Design is challenging and slow
- Expensive
- Not reprogrammable
14
Q
FPGA- about
A
-Field Programmable Gate Array
Ex. FPGA + I2C at NI
15
Q
FPGA- pros
A
- Fast
- Power efficient
- Programmable
16
Q
FPGA- cons
A
- Big
2. Harder to reprogram than a microprocessor
17
Q
DSP- about
A
- A specialized microcontroller
- uses software
- PARALLELISM to increase efficiency
18
Q
DSP- pros
A
- Efficient
2. Programmable
19
Q
Microprocessor- about
A
- a GENERAL PURPOSE processing unit
- runs software
Ex. BeagleBone, desktop computer, Atmel boards, phones, etc.
20
Q
Microprocessor- pros
A
- flexible
- cheap
21
Q
Microprocessor- cons
A
Least efficient
22
Q
Types of microprocessors
A
- MPU
- CPU
- DSP
- System on a Chip (SoC)
- System in a package (SiP)
23
Q
MPU
A
- a STANDALONE CPU
- 32 or 64 bits
24
Q
MCU (microcontroller)- about
A
- a single-chip machine with a processor AND peripherals
- built-in peripherals (RAM, ROM, TC, IO Ports)
- usually no OS
Ex. Atmel board
25
MCU- pros
1. Low power
2. Simple
3. Cheap
26
DSP Chip- about
1. A single chip with a DSP + peripherals for signal processing (ex. Fast RAM)
2. Parallel processing/pipelining
27
DSP chip- pros
1. Fast (low latency)
| 2. Better quality ADC/DAC
28
SoC- about
1. Advanced processing device with ALL PERIPHERALS ON ONE CHIP
2. Usually has an OS
Ex. Smartphones
29
SiP- about
Like SoC
BUT puts components on multiple dies and puts them into a SINGLE PACKAGE
for modularity
Ex. BeagleBone Black
30
ARM
Advanced RISC Machines
RISC- complex actions compiled by several simple instructions
Low energy, low cost
32 DATA registers (NOT memory registers)
Pipelining
31
NVIC priority levels
8 to 256
| We have 16
32
Why do we need pull-up/pull-down resistors?
Without them, GPIO pins are left "floating"
33
DMA
Direct Memory Access
Allows USART to access memory directly
Copies printf statement to RAM where USART will send out data
34
Peripheral DMA Controller
Allows microprocessor to access peripherals (ex. USARTx) by writing to and reading from the memory addresses (even though they are separate devices)
35
Interrupt (definition)
A signal to the processor emitted by hardware or software indicating a event that needs immediate action
36
Types of interrupts
1. External- ex. Button press, serial message received
2. Internal- ex. SysTick, processor fault
3. Exception- ex. Divide by zero
37
Interrupt handling: when a processor detects an interrupt, it...
1. Halts normal execution
2. Saves the current program state
3. Calls the interrupt handler
38
Interrupt Handler Code is usually written by ________
The user to perform a needed task
39
Interrupt Handler code executes until...
Completion
| Then return to the previous program execution
40
Interrupt interface to the processor is required for
1. Internal interrupts- interrupts from the processor (ex. Fault, clock timer)
2. External interrupts- interrupts from devices external to the processor (ex. GPIO pins)
41
What does the NVIC do?
1. Reads all internal and external interrupt requests (IRQ's)
2. Evaluates interrupts in order of priority
3. Calls the interrupt Handler with the highest priority IRQ
42
Interrupt masking
Allows software to ignore specific interruptions
Set via binary values where each bit represents a particular interrupt
43
Most embedded systems are...
Real-time Systems
Need a clock to keep track of deadlines
44
ARM Cortex M4 system timer
Built in with SysTick
| 24-but timer
45
SysTick_Handler
Automatically reloads SYST_CVR With SYST_RVR when SYST_CVR = 0
46
Calculate the elapsed time for SysTick
Elapsed time = NumTicks*(time/tick)
47
Event Driven systems
Use interrupts (instead of edge-triggered polling) to execute time-sensitive instructions
Process
1. Event is detected
2. NVIC evaluates the priority
3. If the interrupt has the highest priority, it is executed in the callback function
4. Otherwise, the interrupt is put into a vector and is executed when it has the highest priority
48
Vectored Interrupts
Context: two interrupts are called such that the execution of their events overlap, and Interrupt 1 has a higher priority that Interrupt 2
1. When Interrupt 2 occurs, it's IRQn is placed in the NVIC Vector in priority order
2. When Interrupt 1 finishes, the IQRn in the vector with the highest priority executes
49
Nested Interrupts
Context: two interrupts are called such that the execution of their events overlap, and Interrupt 2 has a higher priority that Interrupt 1
1. When Interrupt 2 occurs, the NVIC interrupts the Interrupt 1 Handler and executes the Interrupt 2 Handler
2. When Interrupt 2 finishes, the NVIC will resume execution of Interrupt 1
50
About Callbacks
1. AUTOMATICALLY called when an event occurs
2. Must be set up during initialization
3. It is NEVER explicitly called; this means that the cows doesn't need to be "watching" for a condition
51
Interrupt Sources
1. SysTick Timer (internal)
2. EIC (parameters set by user, fancy)
3. GPIO (external, MUST have GPIO Driver Mod; triggered ANY TIME the GPIO pin changes levels)
52
What allows the processor to distinguish between Interrupts?
The IQRn
53
External Device Interface
External Device Interface =
Communication protocol +
Interface Design
54
Communication protocol is typically defined by __________
A standard
Ex. USB, I2C (TWIM), SPI, UART
55
Interface Design is typically defined by ________
The sensor's data sheet or an ICD (interface control doc.)
Describes the info that needs to be sent/received
56
Communication Protocols
1. UART
2. SPI
3. I2C, TWIM
57
UART- about
Universal ASYNCHRONOUS Receiver/Transmitter
1. A common serial port (Putty)
2. Connects devices that are on the same OR different devices
3. EITHER device can transmit data at ANY TIME
4. NO COMMON CLOCK- use settings (baud rate, start/stop bits, parity, etc. to synchronize)
58
UART- pros
1. Asynchronous nature (not always practical to synchronize)
| 2. Can transmit and receive AT THE SAME TIME (separate Rx and Tx lines) controlled by flow control
59
UART- cons
1. Start/stop bits add overhead and decrease efficiency
2. Complex circuitry
3. Clocks that vary slightly distort data
60
SPI- about
Serial Peripheral Interface
1. Connects peripherals ON THE SAME DEVICE
2. SYNCHRONOUS (because peripherals are on the same clock)
3. Master/Slave System (usually microprocessor is the master and it produces a clock signal)
4. Short distance comm. for 1 device
61
SPI- pros
1. Synchronous
| 2. Simple circuitry
62
SPI- cons
Requires a connection for every slave
| a lot of hardware
63
Baud Rate
(Speed)
Clock rate for the sender AND receiver
Data sampled on the rising/falling clock edge
64
I2C / TWIM- about
1. Allows multiple "slave" digital IC's to communicate with one or more masters
2. Short distance comm. for 1 device
3. 2 signal wires to exchange info: SCL (generated by master) + SDA
4. Open drive: can only pull signals LOW and has a pull up resistor to restore signal to HIGH
65
I2C / TWIM- pros
Best of UART and SPI
1. Overcomes asynchronous-related probs
2. Fewer connections than SPI, but no bus contention like UART
66
I2C / TWIM- cons
Some overhead (ACK/NACK per 8 bits)
67
Stop bits
The number of bits required to indicate that transmission has stopped
Note: Data bits are those between the Start and Stop bits
68
Parity
Simplest form of error detection
Parity = sum(data bits) + parity
69
Flow control
Allows the receiver to request that the sender temporarily stop sending data when buffers are getting full
70
T/F Soft deadlines can run on a standard OS
True
71
T/F Hard deadlines can run on a standard OS
False
72
Why can we execute hard deadlines on the Atmel board?
We're not running anything else
73
Period tasks
Tasks must be updated every p periods of time
Ex. Reading and updating the temperature
74
Aperiodic (Sporadic) Tasks
Tasks request the processor at unpredictable times
Handled with Interrupts
Ex. Button press
75
Preemptive Task
External events that interrupt running tasks
Result: unpredictable execution times (jeopardizes real-time deadlines)
76
Non-preemptive Tasks
Tasks are executed until completions
Interrupts must wait for current running task to finish
Result: external events may need to wait a long time before running
77
Static Schedulers
1. Makes decisions at DESIGN TIME
2. Implements decisions at compile time
3. Like pulling
4. Entirely Time Triggered (TT)
78
Dynamic Schedulers
1. Make decisions at RUN TIME
2. Flexible
3. Unaware of resource requirement or dependencies
4. Result: non-deterministic behavior
79
Types of aperiodic scheduling without precedence constraints
1. Earliest Due Deadlines (EDD)
2. Earliest Deadline First (EDF)
3. Least Laxity (LL)
80
EDD- about
Static scheduler
Executes tasks in order of non-decreasing deadlines
Goal: minimize latensss
81
EDD- requirements
All tasks are
1. Independent
2. Known ahead of time (because it's a static scheduler)
3. Ready to execute
82
Earliest Deadline First (EDF)
Dynamic scheduler with preemption
Like EDD, but accounts for varying arrival times
Queues tasks and sorts them by Deadline
83
Least Laxity- about
Dynamic scheduler with preemption
Laxity = Deadline - (current time + duration remaining)
84
Least Laxity- requirements
Knowledge of execution times
85
Precedence
When tasks depend on other tasks
86
Aperiodic scheduling with precedence constraints
Latest Deadline First (LDF)
87
Latest Deadline First (LDF)
Aperiodic
No scheduling constraints
Non-preemptive
Optimal for single processor systems
Puts tasks in a queue based on
1. No successors
2. Latest Deadline
Reverse queue to get execution order
88
Periodic utilization
U = sum(ci / pi)
89
Rate Monotonic Scheduling
RMS
Periodic scheduler
Fixed priorities (shortest period has highest priority)
90
RMS Assumptions
1. all tasks that have hard deadlines are periodic
2. All tasks are independent
3. di = pi for all tasks
4. ci is constant and known for all tasks
5. Time required for context switching is negligible
91
RMS Inequality
u = sum(ci / pi) <= n(2^1/n -1)
GUARANTEES SCHEDULABILITY
92
RMS utilization u for large n
lim = n*(2^1/n - 1) = 0.7
93
Earliest Deadline First (EDF)
Dynamic priorities that change at runtime based on which task has the earliest Deadline
94
RMS- how are priorities determined?
Shortest period has highest priority
95
What do timer counters do?
Count down from a particular register value and generate an interrupt when the register value reaches zero
Ex. SysTick
96
SAM4L Timer Counters
There are 2 with
3 channels that work independently
Connected to a peripheral bus clock
97
T/F: microprocessor often have a built-in GPIO module
False
Microprocessors are standalone processors
98
T/F: The RAM for a microcontroller is part of the microcontroller chip
True
Micro-controllers have the works
99
T/F: if you do not configure an input to use an internal pull-up resistor, that input will read 0 every time it is read
FALSE
Not configuring the input leaves in "floating" so it yields inconsistent results
100
How does the processor communicate printf's to the USART module
DMA
101
Will the processor finish executing configure_console when an interrupt is called?
No
The processor will immediately go to the interrupt Handler
102
Max SysTick Reload Value Register (SYST_RVR):
2^24
| Because SysTick is a 24-but register
103
How do you determine the value for SYST_RVR
(Processor freq.)*(time elapsed)
104
What calls interrupt handlers?
The NVIC
105
T/F: EIC Interrupts can be used be used on any GPIO on the SAM4LC4C microcontroller
FALSE
EIC Interrupts can only be used on pins that are physically to the EIC module
106
To communicate with an external device, you must....
Combine knowledge about:
| Communication Protocol + Interface Design
107
T/F: I2C and SPI are both synchronous
TRUE
108
Synchronous means...
Sharing a common clock
109
SPI Wires
```
SCK (clock)
MOSI (master out slave in)
MISO (mastic in slave out)
SS1
SS2
.
.
.
SSn
```
110
T/F: In I2C, the master must initiate every transmission
TRUE
