MICROPROCESSORS Flashcards

1
Q

Also known as “chip” or “microchip”.

A

INTEGRATED
CIRCUIT

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2
Q

IC is a device that integrates both active components and ____ components.

A

passive

passive components (resistors, capacitors, etc.,)
active components (transistors, diodes, etc.,)

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3
Q

they require energy to turn ON

A

active components

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4
Q

they are always ON

A

passive components

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5
Q

Which of the following is NOT an advantage of an Integrated Circuit?

  • Lower cost
  • Large increase in reliability
  • Drastic increase in size and weight
  • Possible improvement in circuit performance
A

Drastic increase in size and weight

IC’s are made to be small and compact

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6
Q

In Integrated Circuits, a FET functions as an _________

A

Inductor or Coil

Since coils or inductors cannot be fabricated for IC’s as they are size dependent, FETs are used instead

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7
Q

FUNCTIONS of an IC

Op amps, Microwave amps, Microwave amps, Voltage comparators, Small signal amplifier, RF and IF amplifier, Multiplexer, Voltage Regulator

A

Linear or Analog IC

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8
Q

FUNCTIONS of an IC

logic gates, flip flops, counters, clock chips, calculator
chips, memory chip, microprocessor

A

Digital IC

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9
Q

measure of noise immunity

A

NOISE MARGIN (VN)

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10
Q

Nominal Volt

  • BJT
  • Educational use
  • COMMONLY: Schottky TTL
A

TRANSISTOR-TRANSISTOR
LOGIC

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11
Q

The range of voltages between VL(max) and VH(min) are

A

unacceptable

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12
Q

+5V or Vcc

A

NOMINAL VOLT

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13
Q
  • Industry use
  • Easily affected by ESD
  • Lower power consumption and higher fan-out
A

(CMOS)
COMPLEMENTARY METAL OXIDE
SEMICONDUCTOR

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14
Q

ESD stands for ________

A

Electrostatic Discharge

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15
Q

max. # of load ouput gates

A

fan-out

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16
Q

max. # of input gates

A

fan-in

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17
Q
A
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18
Q

Which is true for SPEED-POWER PRODUCT?
* the lower the better
* the higher the better

A

the lower the better

Speed-power product is defined as the product of propagation delay time in ns and power dissipation in mW

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19
Q

the product of propagation delay time in ns and power dissipation in mW

A

SPEED-POWER PRODUCT

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20
Q

the ratio of time a load or circuit is ON compared to the time the load or circuit is OFF

A

DUTY CYCLE

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21
Q

Duty Cycle

In a certain digital waveform, the period is four times the pulse width. The duty cycle is ________.

A

25%

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22
Q

A certain gate draws 1.8µA when its output is HIGH and 3.3µA when its output is LOW. What is the average power dissipation if Vcc is 5V and the gate is operated on a 50% duty cycle?

A. 14 µW
B. 1.27 µW
C. 12.75 µW
D. 5 µW

A

C. 12.75 µW

Pave = ((ICCH + ICCL)/2) * Vcc

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23
Q

For a CMOS gate, which is the best speed-power product?

A. 1.4 pJ
B. 1.6 pJ
C. 2.4 pJ
D. 3.3 pJ

A

1.4 pJ

“the lower, the better”

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24
Q

The active switching element used in all TTL circuits is the ______.
A. bipolar junction transistor (BJT)
B. field-effect transistor (FET)
C. metal-oxide semiconductor field-effect transistor (MOSFET)
D. unijunction transistor (UJ)**

A

bipolar junction transistor (BJT)

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25
Q

Which one of the following is not an example for low power
Schottky TTL?
a. 740L
b. 74LS193
c. 74LS02
d. None of the above

A

740L

with LS - Low Power Schottky

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26
Q

Which of the following logic families has the highest maximum clock frequency?
A. S-TTL
B. AS-TTL
C. HS-TTL
D. HCMOS

A

AS-TTL

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27
Q

Which of the following logic families has the shortest propagation delay?

A. S-TTL
B. AS-TTL
C. HS-TTL
D. HCMOS

A

AS-TTL

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28
Q

Which of the following logic families has the highest noise margin?

A. TTL
B. LS-TTL
C. CMOS
D. HCMOS

A

HCMOS

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29
Q

Which of the logic families allows the highest operating frequency?

A

ECL

Emitter Coupled Logic

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30
Q

Why is the fan-out of CMOS gates frequency dependent?

A. Each CMOS input gate has a specific propagation time and this limits the number of different gates that can be connected to the output of a CMOS gate.

B. When the frequency reaches the critical value, the gate will only be capable of delivering 70% of the normal output voltage and consequently the output power will
be one-half of normal; this defines the upper operating frequency.

C. The higher the number of gates attached to the output, the more frequently they will have to be serviced, thus reducing the frequency at which each will be serviced with an input signal.

D. The input gates of the FETs are predominantly capacitive, and as the signal frequency increases the capacitive loading also increases, thereby limiting the
number of loads that may be attached to the output of the driving gate.*

A

The input gates of the FETs are predominantly capacitive, and as the signal frequency increases the capacitive loading also increases, thereby limiting the
number of loads that may be attached to the output of the driving gate.

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31
Q

In CURRENT SOURCING:
Driving gate _______ current to load gate in HIGH state

A

supplies (source)

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32
Q

In CURRENT SINKING:
Driving gate _______ current from load gate in LOW state

A

receives (sinks)

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33
Q

How many output states does a Totem Pole have?

A

2 output states (HIGH & LOW)

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34
Q

A _________ transistor
controls which transistor is active.

A

phase splitter

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35
Q

Which TTL OUTPUT CONFIGURATION does have this advantages?

  • Changes state faster than open-collector outputs
  • No external components are required
A

TOTEM POLE

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36
Q

________ standard TTL output configuration with a HIGH output and a LOW output transistor, only one of which is active at any time.

A

TOTEM POLE

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37
Q

A circuit that has LOW-state output circuitry, but no HIGH-state output circuitry requires an external pull-up resistor to enable the output to produce a HIGH-state

A

OPEN COLLECTOR:

OPEN COLLECTOR: only 1 output state (LOW)

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38
Q

An OPEN COLLECTOR is used to _________ more current

A

sink

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39
Q

An open collector output can _____ current, but it cannot ______

A) sink, source
B) source,sink
C) supply, source
D) sink, receive

A

sink, source

An open collector output can sink current, but it cannot source

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40
Q

This TTL Output Configuration can can drive their output either HIGH or LOW, but they also have a control input that overrides the effect of the other inputs and places the gate output in a THIRD STATE or HIGH Impedance State

A

TRI-STATE BUFFER

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41
Q

R/W stands for

A

Read/Write

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42
Q

EN stands for

A

Enable

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43
Q

The bipolar TTL logic family that was developed to increase switching speed by preventing transistor saturation is:

A. emitter-coupled logic (ECL)

B. current-mode logic (CML)

C. transistor-transistor logic (TTL)

D. emitter-coupled logic (ECL) and transistor- transistor logic (TTL)

A

emitter-coupled logic (ECL) and transistor- transistor logic (TTL)

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43
Q

An Emitter Coupled Logic has the ______ propagation delay

A

shortest

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44
Q

In a TTL circuit, VOH drops below VOH(min) if an __________ number of load gate inputs are connected.

A

excessive

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45
Q

A classification of IC’s with complexities of 12 to 100 equivalent gates on a chip is known as ___________

A. SSI - Small Scale Integration
B. MSI - Medium Scale Integration
C. LSI - Large Scale Integration
D. VLSI - Very Large Scale Integration

A

MSI

SSI: <30
MSI: 30 - 100
LSI: 100 - 100,000
VLSI: >100,000

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46
Q

Which is not an output state for tristate logic?

A. active HIGH
B. active LOW
C. Low-Impedance
D. High-Impedance

A

Low-Impedance

1 - HIGH, 0 - LOW, Z - High Impedance

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47
Q

The application of feedback in digital electronics is:

A

store data

analog - error correction, digital - data storage

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48
Q

digital circuits that use clock signals to determine the timing of their operations

A

SYNCHRONOUS
LOGIC CIRCUIT

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49
Q

digital circuit that has no memory, timing
and feedback, and depends on instantaneous state

A

COMBINATIONAL LOGIC CIRCUIT

Combinational circuits are usually asynchronous.

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50
Q

an electronic machine that automatically processes data by the use of digital techniques.

A

COMPUTER

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51
Q

A machine that processes data according to a list of internally stored instruction called programs.

A

COMPUTER

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52
Q

ELEMENTS of a microcomputer

“MMIOH”

A

Memory
MPU
I/O
HDD - external device

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53
Q

A parallel line wire used to carry data or electrical signal.

A

BUS

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54
Q

Bus is Composed of?
“(ADC)”

A

Address Bus
Data Bus
Control Bus

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55
Q

Is used to hold data, program or instruction

A

MEMORY

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56
Q

Memory Performance

BWATSi or BWATC

A

Memory BandWidth
Memory Access Time
Memory Capacity

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57
Q

Refers to no. of bytes a memory can transfer

A

Memory Bandwidth

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58
Q

Time memory is accessed until DATA is available

A

Memory Access Time

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59
Q

Memory Size

A

Memory Capacity

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60
Q

_____ = (2^n)(bit width)

A

SIZE = (2n)(bit width)

n = no. of bits
2^n = no. address lines
bit width = no. of data lines

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61
Q

1 nibble = __ bits
2 nibble = __ bits = __ Byte
1 word = __ bits = __ Bytes

A

1 nibble = 4 bits
2 nibble = 8 bits = 1 Byte
1 word = 16 bits = 2 Bytes

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62
Q

Types of Memory:

  • Directly accessible by MPU
  • Used by MPU when performing instructions
A

MAIN/PRIMARY MEMORY OR ADDRESSABLE

TYPES OF MAIN MEMORY
* Read-Only Memory (ROM)
* Random-Access Memory (RAM)

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63
Q
  • program memory
  • Non-volatile (retain data if power is OFF)
  • It’s READ only; holds program and instruction
A

ROM

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64
Q

TYPES OF ROM:

It is Programmed upon manufacturing

A

(ROM) MASKED ROM

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65
Q

TYPES OF ROM:

Programmed by user but ONCE only

A

(PROM) PROGRAMMABLE ROM / ONE TIME PROGRAMMING (OTP)

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66
Q

TYPES OF ROM:

  • Uses UV RAYS to erase whole content
  • Needs to be removed from circuit
A

(EPROM) ERASABLE PROM

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67
Q

TYPES OF ROM:

  • Uses electrical signals available in computer to erase the whole content
  • No need to remove from circuit
A

(EEPROM) ELECTRICALLY EPROM

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68
Q

TYPES OF ROM:

Erases portion of content

A

(EAPROM) ELECTRICALLY ALTERABLE PROM

69
Q

Types of Memory:

  • volatile
  • can be READ or WRITE; holds program and instruction
A

RANDOM-ACCESS MEMORY

70
Q

TYPES OF RAM

Uses flipflops (F/F) to store bit value

A

(SRAM) STATIC RAM

71
Q

TYPES OF RAM

  • Uses capacitors (and transistors) to store bit value
  • Requires periodic refreshing
A

(DRAM) DYNAMIC RAM

REFRESH MODE:
A. BURST – Refresh All
B. DISTRIBUTED – Refresh specific location

72
Q

TYPES OF RAM

FASTER BUT EXPENSIVE

73
Q

TYPES OF RAM

has HIGHER CAPACITY; used in computer memory

74
Q

Types of Memory

  • HIGH SPEED
  • Small amount of memory used to hold frequently accessed data
A

CACHE
MEMORY

IT CAN BE:
i. DATA
ii.INSTRUCTION
iii. BOTH

75
Q

CACHE MEMORY

  • Inside MPU; speed comparable to MPU
  • Faster
A

PRIMARY or LEVEL 1 (L1) CACHE

76
Q

**

  • Between MPU and RAM; speed comparable to SRAM
  • Bulky and slightly slower
A

SECONDARY or LEVEL (L2) CACHE

77
Q

Types of Memory

Used by MPU when computation or process is in progress

A

REGISTERS / PROCESSOR MEMORY

78
Q

Types of Memory

High-speed, large capacity, non-volatile (flashdrive)

A

R / W (READ / WRITE) SEMICON MEMORY

79
Q

EEPROM – Erase at _____ LEVEL
FLASH MEMORY – Erase at _____ LEVEL

A

EEPROM – Erase at BYTE LEVEL
FLASH MEMORY – Erase at BLOCK LEVEL

80
Q
  • It is a FIFO device
  • Used to translate virtual memory into physical memory
A

MEMORY MANAGEMENT UNIT
(MMU)

81
Q

Technique used to transfer data IN/OUT computer system

A

INPUT/OUTPUT
I/O

82
Q

DATA TRANSFER Using Physical I/O

MPU executes program for memory and I/O

A

PROGRAMMED I/O

83
Q

PROGRAMMED I/O

external device must be always ready to accept data

A

UNCONDITIONAL

84
Q

The process of jointly establishing communication is called:

85
Q

PROGRAMMED I/O

uses handshake

A

CONDITIONAL

86
Q

DATA TRANSFER Using Physical I/O

I/O space is separated to memory space

A

STANDARD / ISOLATED I/O

87
Q

DATA TRANSFER Using Physical I/O

I/O Space is within the memory space and uses Address Bits (MSB) to access value

A

. MEMORY-MAPPED I/O (MMIO)

88
Q

DATA TRANSFER Using Physical I/O

a device initiates I/O transfer

A

INTERRUPT I/O

89
Q

INTERRUPT I/O

initiated by external device

A

EXTERNAL INTERRUPT

90
Q

INTERRUPT I/O

initiated by MPU itself

A

INTERNAL INTERRUPT

91
Q

A basic computer does not include:
A. an arithmetic logic unit
B. a control unit
C. peripheral units
D. a memory unit

A

pheripheral units

external devices

91
Q

Select the statement that best describes Read-Only Memory (ROM).

A. nonvolatile, used to store information that changes during system operation

B. nonvolatile, used to store information that does not change during system
operation

C. volatile, used to store information that changes during system operation

D. volatile, used to store information that does not change during system operation*

A

ROM - nonvolatile, used to store information that does not change during system operation

92
Q

Dynamic memory cells store a data bit in a ______.

93
Q

Static memory cells store a data bit in a ______.

94
Q

A major disadvantage of the mask ROM is that it:

A. is time consuming to change the stored data when system requirements change

B. is very expensive to change the stored data when system requirements change

C. cannot be reprogrammed if stored data needs to be changed

D. has an extremely short life expectancy and requires frequent replacement

A

cannot be reprogrammed if stored data needs to be changed

95
Q

Which of the following computer memories is fastest?
A. Cache
B. Primary
C. Mass storage
D. Off line back up

A

Cache

A. Cache - 1st
B. Primary - 2nd
C. Mass storage - 3rd
D. Off line back up - 4th

96
Q

Most devices are interfaced to a bus with _______. It’s also a type of circuit used at the interface point of an input port.

A. totem-pole outputs
B. tri-state buffers
C. pnp transistor
D. resistors

A

tri-state buffers

input port - tri-state buffers
output port - latch

97
Q

An I/O processor control the flow of information between:

A. cache memory and I/O devices
B. main memory and I/O devices
C. 1 Two I/O devices
D. cache and main memories

A

main memory and I/O devices

98
Q

Polling is the method used for:

A. determining the state of a microprocessor

B. establishing communication between CPU and a peripheral

C. establishing a priority for communication with several peripherals

D. determining the next instrcution

A

establishing a priority for communication with several peripherals

Polling
- periodically checks the device status
- best used when no priorities

99
Q

The technique of assigning a memory address to each I/O device in the computer
system is called:
A. memory-mapped I/O
B. ported I/O
C. dedicated I/O
D. wired I/O

A

memory-mapped I/O

100
Q

a device that can be programmed with series of
instructions to perform specified functions of data.

A

MICROPROCESSOR (MPU)

101
Q

ELEMENTS OF MPU

ABCR

A
  • Arithmetic & Logic Unit (ALU)
  • Bus Interface Unit (BIU)
  • Control Unit (CU)
  • Registers

ALU (Arithmetic & Logic Unit)- define size of MPU; computational engine
CU (Control Unit)- direct sequence of operation; select which elements are needed
BIU (Bus Interface Unit)- performs memory addressing

102
Q

(CISC) Complex Instruction Set Computer
* Single Bus Architecture
* Used by MPU (Multitasking)
* FETCH-EXECUTE

A

VON NEUMANN
ARCHITECTURE

103
Q

(RISC) Reduced Instruction Set Computer
* Dual Bus Architecture
* Used by MCU (1 task at a time)

A

HARVARD
ARCHITECTURE

104
Q

SoC means

A

System on a Chip (SoC)

105
Q
  • complete package in a single chip
  • employed on embedded system
  • ROM CAPACITY > RAM CAPACITY (in kB)
A

MICROCONTROLLER (MCU)

106
Q

Which of the following are the three basic sections of a microprocessor unit?

A. operand, register, and arithmetic/logic unit (ALU)

B. control and timing, register, and arithmetic/ logic unit (ALU)

C. control and timing, register, and memory

D. arithmetic/logic unit (ALU), memory, and input/output

A

control and timing, register, and arithmetic/logic unit (ALU)

107
Q

What is occurring when two or more sources of data attempt to use the same bus?
A. Bus contention
B. Direct memory access
C. Bus interruption
D. PPI

A

Bus contention

108
Q

The _____ ensures that only one IC is active at a time to avoid a bus conflict caused by two ICs writing different data to the same bus.

A. control bus
B. control instructions
C. address decoder
D. CPU

A

address decoder

109
Q

Microprocessors and memory IC’s are generally designed to drive only a single TTL load. Therefore, if several inputs are being driven from the same bus, any memory IC must be:

A. buffered
B. decoded
C. addressed
D. stored

110
Q

Under Interrupt I/O, an external device can force the microcomputer system to stop executing the current program temporarily so that it can execute another program known as the:

A. internal interrupt
B. interrupt service routine
C. sub-routine instruction
D. call delay instruction

A

interrupt service routine

111
Q

A register in the microprocessor that keeps track of the answer or results of any arithmetic or logic operation is the:

A. stack register
B. program counter
C. instruction pointer
D. accumulator

A

accumulator

112
Q

Indicates the status of an operation through flags

A

STATUS REGISTER

113
Q

an indicator that uses 1 or 0

114
Q

6 BASIC FLAGS (cannot be changed by the user):

CONDITIONAL FLAGS

A
  • Z (Zero Flag)
  • O (Overflow Flag)
  • S (Sign Flag)
  • P (Parity Flag)
  • C (Carry Flag)
  • H (Hot-Carry)
115
Q

Flags that can be changed by the user (DTI)

CONTROL FLAGS

A
  • Direction Flag – for strings
  • Trap Flag – for interpreter (execute instruction line by line)
  • Interrupt Flag
116
Q

FIFO is formed by an arrangement of :

A. diodes
B. transistors
C. MOS cells
D. shift registers

A

shift registers

117
Q

A programming language that uses English-like words and has a one-to-one correspondence to machine language refers to

A. assembly language
B. Firmware
C. high-level language
D. interpreter

A

assembly language

118
Q

A microprocessor is generally:

A. single chip SSI

B. single chip MSI

C. single chip LSI

D. any of the above

A

single chip LSI

MPU - LSI

119
Q

The remaining address line of _____ bus is decoded to generate chip select signal.

A. Data
B. Address
C. Control bus
D. Both (a) and (b)

120
Q

Used to store critical pieces of data during subroutines and interrupts:

121
Q

Zero address instruction format is used for
Von-Neuman architecture
RISC architecture
CISC architecture
Stack-organized architecture

A

Stack-organized architecture

122
Q

________ is usually the first level of memory access by the microprocessor

A

Cache Memory

123
Q

Microprocessor reference that are available in the cache are called______

A

Cache hits

not available -cache misses

124
Q

Which are the two main components of the CPU?

A

Control unit and ALU

125
Q

Registers, which are partially visible to users and used to hold conditional, are known as

A

General purpose register

126
Q

The metal disks, which are permanently housed in, sealed and contamination free containers are called

A

Winchester disk

127
Q

The instructions for starting the computer are house on

A

Read only memory chip

128
Q

The ALU of a computer normally contains a number of high speed storage element called

129
Q

To locate a data item for storage is

130
Q

Which of the following terms is the most closely related to main memory?
a. Non volatile
b. Permanent
c. Control unit
d. Temporary

A

d. Temporary

131
Q

The register section is related to________of the computer

A

Main memory

132
Q

In Microprocessor one of the operands holds a special register called

A

Accumulator

133
Q

a subsystem that transfer data between computer components inside a computer or between computer:

134
Q

Which memory is used to hold the address of the data stored in the cache

A

Associative memory

135
Q

A certain SRAM has CS = 0 , WE = 0 and OE = 1. In which of the following modes this SRAM is operating

136
Q

The first modern computer was called

137
Q

The time required to refresh a typical DRAM is

138
Q

The no. of address lines required to address a memory of size 32 K is

139
Q

A floppy disk is used in a microprocessor based system as

A

I/O Device

140
Q

A system of letters ,symbols used by the microprocessor manufacturers as an abbreviated form of an instruction is called

141
Q

Which microprocessor architecture is used in most personal computers and servers today?

A

CISC(Complex Instruction Set Computing)

Von Neumann

142
Q

The microprocessor’s clock speed is measured in:

A

Gigahertz (GHz)

143
Q

Which microprocessor architecture is commonly used in mobile devices and embedded systems?

A

ARM (Advanced RISC Machine)

144
Q

The concept of “big-endian” and “little-endian” relates to:

A

Data storage order in memory

145
Q

In a microprocessor, the “stack” is typically used for:

A

Temporary data storage and managing subroutine calls

146
Q

Which microprocessor mode allows privileged operations and direct access to hardware?

A

Kernel Mode

147
Q

Which microprocessor feature allows multiple instructions to be executed simultaneously, improving performance?

A

Pipelining

148
Q

What is the Von Neumann Architecture?

A

SISD(Single Instruction, Single Data)

149
Q

Most common access technique in CPUs

150
Q

Two most common stack operators

A

Push and Pop

151
Q

Stack-organized computeruses instruction of _______

A

Zero Addressing

152
Q

Speed of Supercomputer is measured in

A

FLOPS

Floating Points Operations Per Second

153
Q

An early form of Random Access Memory (RAM)

A

Magnetic Core Memory

154
Q

It is a small-sized type of volatile computer memory that provides high-speed data access to the CPU

A

Cache Memory

155
Q

It is a type of non-volatile memory that uses a thin film of a magnetic material to hold small magnetized areas, known as bubbles, which each store a bit of data.

A

magnetic Bubble Memory

156
Q

Widely used as main computer’s main memory

157
Q

Permanent memory of a computer

158
Q

The electronic circuitry that executes instructions in a computer programme is known as

A

central processing unit (CPU)

159
Q

Operations mainly performed by RAM

A

Read and Write

160
Q

The organization and inter connection of the various components of computer system is

A

Architecture

161
Q

is a special type of memory that works like both RAM and ROM

A

Flash Memory

162
Q

Smallest and fastest memory in computer

A

Register memory

faster than cache

163
Q

Arrange the following computer memory types from fastest to slowest
speed:
(A) Hard Disk
(B) Main Memory (RAM)
(C) CD-ROM
(D) CPU Registers
(E) Cache Memory

A

D, E, B, A, C

164
Q

POST

A

Power-On Self-Test

165
Q

The first instructor of bootstrap loader program of an operating system is stored in

A

BIOS(Basic Input/Output System)

166
Q

A small program that is responsible for loading the operating system into memory

A

Bootstrap Loader

167
Q

A tiny bootsrap loader program is situated in

168
Q

Bits used when cache location is updated