MICROPROCESSORS Flashcards
Also known as “chip” or “microchip”.
INTEGRATED
CIRCUIT
IC is a device that integrates both active components and ____ components.
passive
passive components (resistors, capacitors, etc.,)
active components (transistors, diodes, etc.,)
they require energy to turn ON
active components
they are always ON
passive components
Which of the following is NOT an advantage of an Integrated Circuit?
- Lower cost
- Large increase in reliability
- Drastic increase in size and weight
- Possible improvement in circuit performance
Drastic increase in size and weight
IC’s are made to be small and compact
In Integrated Circuits, a FET functions as an _________
Inductor or Coil
Since coils or inductors cannot be fabricated for IC’s as they are size dependent, FETs are used instead
FUNCTIONS of an IC
Op amps, Microwave amps, Microwave amps, Voltage comparators, Small signal amplifier, RF and IF amplifier, Multiplexer, Voltage Regulator
Linear or Analog IC
FUNCTIONS of an IC
logic gates, flip flops, counters, clock chips, calculator
chips, memory chip, microprocessor
Digital IC
measure of noise immunity
NOISE MARGIN (VN)
Nominal Volt
- BJT
- Educational use
- COMMONLY: Schottky TTL
TRANSISTOR-TRANSISTOR
LOGIC
The range of voltages between VL(max) and VH(min) are
unacceptable
+5V or Vcc
NOMINAL VOLT
- Industry use
- Easily affected by ESD
- Lower power consumption and higher fan-out
(CMOS)
COMPLEMENTARY METAL OXIDE
SEMICONDUCTOR
ESD stands for ________
Electrostatic Discharge
max. # of load ouput gates
fan-out
max. # of input gates
fan-in
Which is true for SPEED-POWER PRODUCT?
* the lower the better
* the higher the better
the lower the better
Speed-power product is defined as the product of propagation delay time in ns and power dissipation in mW
the product of propagation delay time in ns and power dissipation in mW
SPEED-POWER PRODUCT
the ratio of time a load or circuit is ON compared to the time the load or circuit is OFF
DUTY CYCLE
Duty Cycle
In a certain digital waveform, the period is four times the pulse width. The duty cycle is ________.
25%
A certain gate draws 1.8µA when its output is HIGH and 3.3µA when its output is LOW. What is the average power dissipation if Vcc is 5V and the gate is operated on a 50% duty cycle?
A. 14 µW
B. 1.27 µW
C. 12.75 µW
D. 5 µW
C. 12.75 µW
Pave = ((ICCH + ICCL)/2) * Vcc
For a CMOS gate, which is the best speed-power product?
A. 1.4 pJ
B. 1.6 pJ
C. 2.4 pJ
D. 3.3 pJ
1.4 pJ
“the lower, the better”
The active switching element used in all TTL circuits is the ______.
A. bipolar junction transistor (BJT)
B. field-effect transistor (FET)
C. metal-oxide semiconductor field-effect transistor (MOSFET)
D. unijunction transistor (UJ)**
bipolar junction transistor (BJT)
Which one of the following is not an example for low power
Schottky TTL?
a. 740L
b. 74LS193
c. 74LS02
d. None of the above
740L
with LS - Low Power Schottky
Which of the following logic families has the highest maximum clock frequency?
A. S-TTL
B. AS-TTL
C. HS-TTL
D. HCMOS
AS-TTL
Which of the following logic families has the shortest propagation delay?
A. S-TTL
B. AS-TTL
C. HS-TTL
D. HCMOS
AS-TTL
Which of the following logic families has the highest noise margin?
A. TTL
B. LS-TTL
C. CMOS
D. HCMOS
HCMOS
Which of the logic families allows the highest operating frequency?
ECL
Emitter Coupled Logic
Why is the fan-out of CMOS gates frequency dependent?
A. Each CMOS input gate has a specific propagation time and this limits the number of different gates that can be connected to the output of a CMOS gate.
B. When the frequency reaches the critical value, the gate will only be capable of delivering 70% of the normal output voltage and consequently the output power will
be one-half of normal; this defines the upper operating frequency.
C. The higher the number of gates attached to the output, the more frequently they will have to be serviced, thus reducing the frequency at which each will be serviced with an input signal.
D. The input gates of the FETs are predominantly capacitive, and as the signal frequency increases the capacitive loading also increases, thereby limiting the
number of loads that may be attached to the output of the driving gate.*
The input gates of the FETs are predominantly capacitive, and as the signal frequency increases the capacitive loading also increases, thereby limiting the
number of loads that may be attached to the output of the driving gate.
In CURRENT SOURCING:
Driving gate _______ current to load gate in HIGH state
supplies (source)
In CURRENT SINKING:
Driving gate _______ current from load gate in LOW state
receives (sinks)
How many output states does a Totem Pole have?
2 output states (HIGH & LOW)
A _________ transistor
controls which transistor is active.
phase splitter
Which TTL OUTPUT CONFIGURATION does have this advantages?
- Changes state faster than open-collector outputs
- No external components are required
TOTEM POLE
________ standard TTL output configuration with a HIGH output and a LOW output transistor, only one of which is active at any time.
TOTEM POLE
A circuit that has LOW-state output circuitry, but no HIGH-state output circuitry requires an external pull-up resistor to enable the output to produce a HIGH-state
OPEN COLLECTOR:
OPEN COLLECTOR: only 1 output state (LOW)
An OPEN COLLECTOR is used to _________ more current
sink
An open collector output can _____ current, but it cannot ______
A) sink, source
B) source,sink
C) supply, source
D) sink, receive
sink, source
An open collector output can sink current, but it cannot source
This TTL Output Configuration can can drive their output either HIGH or LOW, but they also have a control input that overrides the effect of the other inputs and places the gate output in a THIRD STATE or HIGH Impedance State
TRI-STATE BUFFER
R/W stands for
Read/Write
EN stands for
Enable
The bipolar TTL logic family that was developed to increase switching speed by preventing transistor saturation is:
A. emitter-coupled logic (ECL)
B. current-mode logic (CML)
C. transistor-transistor logic (TTL)
D. emitter-coupled logic (ECL) and transistor- transistor logic (TTL)
emitter-coupled logic (ECL) and transistor- transistor logic (TTL)
An Emitter Coupled Logic has the ______ propagation delay
shortest
In a TTL circuit, VOH drops below VOH(min) if an __________ number of load gate inputs are connected.
excessive
A classification of IC’s with complexities of 12 to 100 equivalent gates on a chip is known as ___________
A. SSI - Small Scale Integration
B. MSI - Medium Scale Integration
C. LSI - Large Scale Integration
D. VLSI - Very Large Scale Integration
MSI
SSI: <30
MSI: 30 - 100
LSI: 100 - 100,000
VLSI: >100,000
Which is not an output state for tristate logic?
A. active HIGH
B. active LOW
C. Low-Impedance
D. High-Impedance
Low-Impedance
1 - HIGH, 0 - LOW, Z - High Impedance
The application of feedback in digital electronics is:
store data
analog - error correction, digital - data storage
digital circuits that use clock signals to determine the timing of their operations
SYNCHRONOUS
LOGIC CIRCUIT
digital circuit that has no memory, timing
and feedback, and depends on instantaneous state
COMBINATIONAL LOGIC CIRCUIT
Combinational circuits are usually asynchronous.
an electronic machine that automatically processes data by the use of digital techniques.
COMPUTER
A machine that processes data according to a list of internally stored instruction called programs.
COMPUTER
ELEMENTS of a microcomputer
“MMIOH”
Memory
MPU
I/O
HDD - external device
A parallel line wire used to carry data or electrical signal.
BUS
Bus is Composed of?
“(ADC)”
Address Bus
Data Bus
Control Bus
Is used to hold data, program or instruction
MEMORY
Memory Performance
BWATSi or BWATC
Memory BandWidth
Memory Access Time
Memory Capacity
Refers to no. of bytes a memory can transfer
Memory Bandwidth
Time memory is accessed until DATA is available
Memory Access Time
Memory Size
Memory Capacity
_____ = (2^n)(bit width)
SIZE = (2n)(bit width)
n = no. of bits
2^n = no. address lines
bit width = no. of data lines
1 nibble = __ bits
2 nibble = __ bits = __ Byte
1 word = __ bits = __ Bytes
1 nibble = 4 bits
2 nibble = 8 bits = 1 Byte
1 word = 16 bits = 2 Bytes
Types of Memory:
- Directly accessible by MPU
- Used by MPU when performing instructions
MAIN/PRIMARY MEMORY OR ADDRESSABLE
TYPES OF MAIN MEMORY
* Read-Only Memory (ROM)
* Random-Access Memory (RAM)
- program memory
- Non-volatile (retain data if power is OFF)
- It’s READ only; holds program and instruction
ROM
TYPES OF ROM:
It is Programmed upon manufacturing
(ROM) MASKED ROM
TYPES OF ROM:
Programmed by user but ONCE only
(PROM) PROGRAMMABLE ROM / ONE TIME PROGRAMMING (OTP)
TYPES OF ROM:
- Uses UV RAYS to erase whole content
- Needs to be removed from circuit
(EPROM) ERASABLE PROM
TYPES OF ROM:
- Uses electrical signals available in computer to erase the whole content
- No need to remove from circuit
(EEPROM) ELECTRICALLY EPROM
TYPES OF ROM:
Erases portion of content
(EAPROM) ELECTRICALLY ALTERABLE PROM
Types of Memory:
- volatile
- can be READ or WRITE; holds program and instruction
RANDOM-ACCESS MEMORY
TYPES OF RAM
Uses flipflops (F/F) to store bit value
(SRAM) STATIC RAM
TYPES OF RAM
- Uses capacitors (and transistors) to store bit value
- Requires periodic refreshing
(DRAM) DYNAMIC RAM
REFRESH MODE:
A. BURST – Refresh All
B. DISTRIBUTED – Refresh specific location
TYPES OF RAM
FASTER BUT EXPENSIVE
SRAM
TYPES OF RAM
has HIGHER CAPACITY; used in computer memory
DRAM
Types of Memory
- HIGH SPEED
- Small amount of memory used to hold frequently accessed data
CACHE
MEMORY
IT CAN BE:
i. DATA
ii.INSTRUCTION
iii. BOTH
CACHE MEMORY
- Inside MPU; speed comparable to MPU
- Faster
PRIMARY or LEVEL 1 (L1) CACHE
**
- Between MPU and RAM; speed comparable to SRAM
- Bulky and slightly slower
SECONDARY or LEVEL (L2) CACHE
Types of Memory
Used by MPU when computation or process is in progress
REGISTERS / PROCESSOR MEMORY
Types of Memory
High-speed, large capacity, non-volatile (flashdrive)
R / W (READ / WRITE) SEMICON MEMORY
EEPROM – Erase at _____ LEVEL
FLASH MEMORY – Erase at _____ LEVEL
EEPROM – Erase at BYTE LEVEL
FLASH MEMORY – Erase at BLOCK LEVEL
- It is a FIFO device
- Used to translate virtual memory into physical memory
MEMORY MANAGEMENT UNIT
(MMU)
Technique used to transfer data IN/OUT computer system
INPUT/OUTPUT
I/O
DATA TRANSFER Using Physical I/O
MPU executes program for memory and I/O
PROGRAMMED I/O
PROGRAMMED I/O
external device must be always ready to accept data
UNCONDITIONAL
The process of jointly establishing communication is called:
handshake
PROGRAMMED I/O
uses handshake
CONDITIONAL
DATA TRANSFER Using Physical I/O
I/O space is separated to memory space
STANDARD / ISOLATED I/O
DATA TRANSFER Using Physical I/O
I/O Space is within the memory space and uses Address Bits (MSB) to access value
. MEMORY-MAPPED I/O (MMIO)
DATA TRANSFER Using Physical I/O
a device initiates I/O transfer
INTERRUPT I/O
INTERRUPT I/O
initiated by external device
EXTERNAL INTERRUPT
INTERRUPT I/O
initiated by MPU itself
INTERNAL INTERRUPT
A basic computer does not include:
A. an arithmetic logic unit
B. a control unit
C. peripheral units
D. a memory unit
pheripheral units
external devices
Select the statement that best describes Read-Only Memory (ROM).
A. nonvolatile, used to store information that changes during system operation
B. nonvolatile, used to store information that does not change during system
operation
C. volatile, used to store information that changes during system operation
D. volatile, used to store information that does not change during system operation*
ROM - nonvolatile, used to store information that does not change during system operation
Dynamic memory cells store a data bit in a ______.
capacitor
Static memory cells store a data bit in a ______.
flip-flop
A major disadvantage of the mask ROM is that it:
A. is time consuming to change the stored data when system requirements change
B. is very expensive to change the stored data when system requirements change
C. cannot be reprogrammed if stored data needs to be changed
D. has an extremely short life expectancy and requires frequent replacement
cannot be reprogrammed if stored data needs to be changed
Which of the following computer memories is fastest?
A. Cache
B. Primary
C. Mass storage
D. Off line back up
Cache
A. Cache - 1st
B. Primary - 2nd
C. Mass storage - 3rd
D. Off line back up - 4th
Most devices are interfaced to a bus with _______. It’s also a type of circuit used at the interface point of an input port.
A. totem-pole outputs
B. tri-state buffers
C. pnp transistor
D. resistors
tri-state buffers
input port - tri-state buffers
output port - latch
An I/O processor control the flow of information between:
A. cache memory and I/O devices
B. main memory and I/O devices
C. 1 Two I/O devices
D. cache and main memories
main memory and I/O devices
Polling is the method used for:
A. determining the state of a microprocessor
B. establishing communication between CPU and a peripheral
C. establishing a priority for communication with several peripherals
D. determining the next instrcution
establishing a priority for communication with several peripherals
Polling
- periodically checks the device status
- best used when no priorities
The technique of assigning a memory address to each I/O device in the computer
system is called:
A. memory-mapped I/O
B. ported I/O
C. dedicated I/O
D. wired I/O
memory-mapped I/O
a device that can be programmed with series of
instructions to perform specified functions of data.
MICROPROCESSOR (MPU)
ELEMENTS OF MPU
ABCR
- Arithmetic & Logic Unit (ALU)
- Bus Interface Unit (BIU)
- Control Unit (CU)
- Registers
ALU (Arithmetic & Logic Unit)- define size of MPU; computational engine
CU (Control Unit)- direct sequence of operation; select which elements are needed
BIU (Bus Interface Unit)- performs memory addressing
(CISC) Complex Instruction Set Computer
* Single Bus Architecture
* Used by MPU (Multitasking)
* FETCH-EXECUTE
VON NEUMANN
ARCHITECTURE
(RISC) Reduced Instruction Set Computer
* Dual Bus Architecture
* Used by MCU (1 task at a time)
HARVARD
ARCHITECTURE
SoC means
System on a Chip (SoC)
- complete package in a single chip
- employed on embedded system
- ROM CAPACITY > RAM CAPACITY (in kB)
MICROCONTROLLER (MCU)
Which of the following are the three basic sections of a microprocessor unit?
A. operand, register, and arithmetic/logic unit (ALU)
B. control and timing, register, and arithmetic/ logic unit (ALU)
C. control and timing, register, and memory
D. arithmetic/logic unit (ALU), memory, and input/output
control and timing, register, and arithmetic/logic unit (ALU)
What is occurring when two or more sources of data attempt to use the same bus?
A. Bus contention
B. Direct memory access
C. Bus interruption
D. PPI
Bus contention
The _____ ensures that only one IC is active at a time to avoid a bus conflict caused by two ICs writing different data to the same bus.
A. control bus
B. control instructions
C. address decoder
D. CPU
address decoder
Microprocessors and memory IC’s are generally designed to drive only a single TTL load. Therefore, if several inputs are being driven from the same bus, any memory IC must be:
A. buffered
B. decoded
C. addressed
D. stored
buffered
Under Interrupt I/O, an external device can force the microcomputer system to stop executing the current program temporarily so that it can execute another program known as the:
A. internal interrupt
B. interrupt service routine
C. sub-routine instruction
D. call delay instruction
interrupt service routine
A register in the microprocessor that keeps track of the answer or results of any arithmetic or logic operation is the:
A. stack register
B. program counter
C. instruction pointer
D. accumulator
accumulator
Indicates the status of an operation through flags
STATUS REGISTER
an indicator that uses 1 or 0
FLAGS
6 BASIC FLAGS (cannot be changed by the user):
CONDITIONAL FLAGS
- Z (Zero Flag)
- O (Overflow Flag)
- S (Sign Flag)
- P (Parity Flag)
- C (Carry Flag)
- H (Hot-Carry)
Flags that can be changed by the user (DTI)
CONTROL FLAGS
- Direction Flag – for strings
- Trap Flag – for interpreter (execute instruction line by line)
- Interrupt Flag
FIFO is formed by an arrangement of :
A. diodes
B. transistors
C. MOS cells
D. shift registers
shift registers
A programming language that uses English-like words and has a one-to-one correspondence to machine language refers to
A. assembly language
B. Firmware
C. high-level language
D. interpreter
assembly language
A microprocessor is generally:
A. single chip SSI
B. single chip MSI
C. single chip LSI
D. any of the above
single chip LSI
MPU - LSI
The remaining address line of _____ bus is decoded to generate chip select signal.
A. Data
B. Address
C. Control bus
D. Both (a) and (b)
address
Used to store critical pieces of data during subroutines and interrupts:
Stack
Zero address instruction format is used for
Von-Neuman architecture
RISC architecture
CISC architecture
Stack-organized architecture
Stack-organized architecture
________ is usually the first level of memory access by the microprocessor
Cache Memory
Microprocessor reference that are available in the cache are called______
Cache hits
not available -cache misses
Which are the two main components of the CPU?
Control unit and ALU
Registers, which are partially visible to users and used to hold conditional, are known as
General purpose register
The metal disks, which are permanently housed in, sealed and contamination free containers are called
Winchester disk
The instructions for starting the computer are house on
Read only memory chip
The ALU of a computer normally contains a number of high speed storage element called
Registers
To locate a data item for storage is
Fetch
Which of the following terms is the most closely related to main memory?
a. Non volatile
b. Permanent
c. Control unit
d. Temporary
d. Temporary
The register section is related to________of the computer
Main memory
In Microprocessor one of the operands holds a special register called
Accumulator
a subsystem that transfer data between computer components inside a computer or between computer:
Bus
Which memory is used to hold the address of the data stored in the cache
Associative memory
A certain SRAM has CS = 0 , WE = 0 and OE = 1. In which of the following modes this SRAM is operating
Write
The first modern computer was called
ENIAC
The time required to refresh a typical DRAM is
2-4 ms
The no. of address lines required to address a memory of size 32 K is
15
A floppy disk is used in a microprocessor based system as
I/O Device
A system of letters ,symbols used by the microprocessor manufacturers as an abbreviated form of an instruction is called
mnemonic
Which microprocessor architecture is used in most personal computers and servers today?
CISC(Complex Instruction Set Computing)
Von Neumann
The microprocessor’s clock speed is measured in:
Gigahertz (GHz)
Which microprocessor architecture is commonly used in mobile devices and embedded systems?
ARM (Advanced RISC Machine)
The concept of “big-endian” and “little-endian” relates to:
Data storage order in memory
In a microprocessor, the “stack” is typically used for:
Temporary data storage and managing subroutine calls
Which microprocessor mode allows privileged operations and direct access to hardware?
Kernel Mode
Which microprocessor feature allows multiple instructions to be executed simultaneously, improving performance?
Pipelining
What is the Von Neumann Architecture?
SISD(Single Instruction, Single Data)
Most common access technique in CPUs
LIFO
Two most common stack operators
Push and Pop
Stack-organized computeruses instruction of _______
Zero Addressing
Speed of Supercomputer is measured in
FLOPS
Floating Points Operations Per Second
An early form of Random Access Memory (RAM)
Magnetic Core Memory
It is a small-sized type of volatile computer memory that provides high-speed data access to the CPU
Cache Memory
It is a type of non-volatile memory that uses a thin film of a magnetic material to hold small magnetized areas, known as bubbles, which each store a bit of data.
magnetic Bubble Memory
Widely used as main computer’s main memory
DRAM
Permanent memory of a computer
ROM
The electronic circuitry that executes instructions in a computer programme is known as
central processing unit (CPU)
Operations mainly performed by RAM
Read and Write
The organization and inter connection of the various components of computer system is
Architecture
is a special type of memory that works like both RAM and ROM
Flash Memory
Smallest and fastest memory in computer
Register memory
faster than cache
Arrange the following computer memory types from fastest to slowest
speed:
(A) Hard Disk
(B) Main Memory (RAM)
(C) CD-ROM
(D) CPU Registers
(E) Cache Memory
D, E, B, A, C
POST
Power-On Self-Test
The first instructor of bootstrap loader program of an operating system is stored in
BIOS(Basic Input/Output System)
A small program that is responsible for loading the operating system into memory
Bootstrap Loader
A tiny bootsrap loader program is situated in
ROM
Bits used when cache location is updated
Dirty bit