Memory and Cache

Question 1

What is Fully Associative Cache?

Answer 1

Fully Associative Cache can map a memory address to any block in the cache

Question 2

What is Set Associative Cache?

Answer 2

Trade-off between direct mapped cache and the fully associative cache, divided into groups of blocks called sets, where each memory address is mapped to only one set (data can be placed anywhere within this set)

Question 3

How does a Set Associative Cache differ from both Direct Mapped and Fully Associative Caches?

Answer 3

Set associative divides cache into sets, each address maps to one set but can be placed in any block within that set, balancing flexibility and efficiency

Question 4

What are the trade-offs of using a Fully Associative Cache compared to Direct Mapping?

Answer 4

Fully associative allows any data to be stored anywhere, increasing flexibility at the cost of complexity and higher hardware requirements

Question 5

What is temporal locality, and how does it influence what should be stored in the cache?

Answer 5

Temporal locality suggests that recently accessed data will likely be accessed again soon, such data should be kept in a cache

Question 6

What is direct mapping in cache architecture?

Answer 6

A method where each memory location maps to exactly one location in the cache

Question 7

Define the principle of locality in relation to cache performance

Answer 7

Locality refers to the tendency of a program to access a relatively small portion of its address space at any given time, typically temporal and spatial locality

Question 8

What is the difference in access times and costs between Dynamic RAM (DRAM) and Flash superconductor memory?

Answer 8

DRAM access time: 50ns to 70ns; Cost: $10 to $20 per GB; Flash access time: 5,000ns to 50,000ns; Cost: $0.75 to $1 per GB

Question 9

Explain how invalid blocks in a cache can be reused for new data

Answer 9

Invalid blocks can be filled with new data without affecting existing valid data, making efficient use of cache space

Question 10

In what scenarios are larger block sizes beneficial for cache performance?

Answer 10

When accessing contiguous data items, larger blocks can exploit spatial locality, reducing the number of cache misses

Question 11

What impact does miss penalty have on Average Memory Access Time (AMAT)?

Answer 11

Higher miss penalty increases AMAT, leading to slower overall performance as more time is spent fetching data from memory

Question 12

What are the components that make up Average Memory Access Time (AMAT)? (Formula)

Answer 12

AMAT = hit time + (miss rate × miss penalty)

Question 13

How do you place a new value in a cache?

Answer 13

By using mapping techniques such as direct mapping, fully associative, or set associative

Question 14

What factors can be used to evaluate the performance of cache?

Answer 14

• Cache hit rate
• Miss rate, hit time
• Miss penalty
• Average Memory Access Time (AMAT)

Question 15

What are the access times and costs associated with Static RAM (SRAM)?

Answer 15

Access time: 0.5ns to 2.5ns; Cost: $500 to $1000 per GB

Question 16

What is spatial locality, and how does it affect cache design?

Answer 16

Spatial locality suggests that items near those accessed recently will likely be accessed soon; it influences the size of cache blocks

Question 17

How does hit time affect the overall performance of a caching system?

Answer 17

Lower hit time improves performance by decreasing the time taken to access data from the cache

Question 18

How do you calculate the hit rate in a caching system?

Answer 18

Hit rate = number of cache hits (h) / total data requests (n)

Question 19

How does the size of the cache affect hit and miss rates?

Answer 19

Larger caches typically reduce miss rates by providing more space for data, while smaller caches may lead to more frequent cache misses

Question 20

How does memory and cache impact processor performance?

Answer 20

They significantly reduce the time the CPU spends waiting for data, increasing throughput and speed

Question 21

Describe the structure of a cache’s data block

Answer 21

Each block includes valid bits, tags, and the actual data being cached

Question 22

What is an LRU (Least Recently Used) strategy and how is it implemented in caches?

Answer 22

LRU keeps track of the order of use of blocks and evicts the least recently used block when space is needed

Question 23

How can valid bits help indicate whether data in a cache block is valid?

Answer 23

A valid bit is set to 1 when data is loaded into a cache block, indicating that the data can be used

Question 24

What roles do the index and cache tag play in finding data in the cache?

Answer 24

The index identifies the cache block; the tag verifies that the data in that block corresponds to the requested address

Question 25

How does the memory address map to the cache index using direct mapping?

Answer 25

The memory address is mapped using modulo division by the size of the cache

Question 26

What are the two types of locality and why are they important for cache performance?

Answer 26

Temporal locality (recently accessed items) and spatial locality (nearby items); they help determine what data should be cached to increase hit rates

Question 27

What steps are involved in finding data in a cache?

Answer 27

1. Index a block in the cache
2. Check the valid bit
3. Match the cache tag with the address tag

Question 28

What is the formula for miss rate and how is it derived?

Answer 28

Miss rate = 1 - hit rate = (n - h) / n

Question 29

How does the access time of magnetic disk compare to that of SRAM?

Answer 29

Magnetic disk access time is significantly slower, ranging from 5,000,000ns to 20,000,000ns

Question 30

What is the primary purpose of memory and cache in a computer system?

Answer 30

To store and quickly access data that the CPU needs, enhancing performance and efficiency

Question 31

Describe the block replacement strategies used in associative caches

Answer 31

Replacement strategies include Least Recently Used (LRU), random replacement, and first-in, first-out (FIFO)