Logic Gates and Circuits Flashcards
(22 cards)
x + x and x * x is equal to? Also what is the rule called?
x + x = x, x* x = x (Idenpotent Rule)
What is the rule, where anything + 1 is equal to 1?
x + 1 = 1 , Unit and Zero property
What is the zero property with products (AND GATES)?
x*0 = 0
What is the fancy word for double negation?
Involution x = ((x)’)’
What does the associative rule mean? Does it work for both OR and AND gates?
Yes!
x + ( y + z) = (x + y) + z
x · (y · z) = (x ·y) · z
What is Demorgan’s law.
(x+y)' = x'y' (xy)' = x' + y'
What is the absorption law?
x + xy = x
x · (x + y) = x
What is the operator precedance?
1- Brackets
2- NOT
3- AND
4- OR
What are the common ways to minimize logic circuit?
By using boolean algebra and/or K-maps
What are Minterms and Maxterms?
minterms are when the function’s output is 1 (true). The max term is when the function’s output is 0.
How is the k-map setup?
the k-map must be setup so that only 1 variable changes from one box to the other.
Ex: 00, 01, 11, 10
What are the restrictions of the k-map?
The k-map can only use 4 or 5 variables.
What is a prime implicant?
The prime implicant is the most reduced expression.
What is the difference between SOP and POS.
Sum of products. Example: ABC+A’B+B’C
Product of sums Example: (A+B+C)(A’+B)(B’+C)
How do you simplify using the K-map?
By making groups of 2^n
Groups of 2 -> 1 variable gets dropped
Groups of 4 ->2 variables gets dropped
Group of 8 -> 3 variables gets dropped
Why do people tend to design their circuits using NAND gates?
Because the NAND gates are cheaper to build and they make the circuit easier to physically implement.
How do you deal with extra inputs to a AND logic gate?
By connecting the left over inputs to 1.
How do you deal with extra inputs to a OR logic gate?
By connecting the left over inputs to 0.
How do you implement an AND gate using only NAND?
By using only 2 NAND gates.
Results (gate by gate)
AB->(AB)’->((AB)’)’ -> AB
How do you implement a NOT gate using NAND?
By connecting the same variable to both inputs of the NAND. since, (AA)’ = A’
How do you implement a NOR gate using NAND gates?
By using 3 NAND gates. Using the same principale as the NOT gate, You can get A going into the 2 inputs of the first NAND gate exclusively. You can also do that with B. That way you have A’ and B’ as inputs into the last NAND gate. Which result in (A’B’)’ = A+B
What is the boolean expression for XOR gate?
F = A’B + AB’
