Lesson 1--Review of Computer Architecture

Question 1

Instruction Level Parallelism (ILP)

Answer 1

• -Executing multiple operations simultaneously.
• -Independent of hardware
• -In embedded systems, there is a trade-off between performance and power consumption (decrease clock frequency to save power)

Question 2

Low Instructions Per Cycle (IPC) is a result of…

Answer 2

• -strict sequential semantics

- -instructions stalled for data or resource release by other instructions

Question 3

Pipelining

Answer 3

Used to overlap instructions

Question 4

Pipelines in modern CPUs have the following characteristics

Answer 4

• -execution stages are divided into several steps
• -a later operation can share the resources used by the first operation in previous cycles
• -shared hardware can be pipelined

Question 5

Cycles Per Instruction (CPI)

Answer 5

((cyclespercentage) + (cyclespercentage) + (cycles*percentage) + …)/100

Question 6

For a pipeline that is k stages deep, how many cycles does it take to fill the pipeline?

Answer 6

k - 1

Question 7

VLIW

Answer 7

Very Long Instruction Word

Question 8

How many operations can a VEX processor have in each cycle using VLIW?

Answer 8

4

Question 9

In a VEX processor, what are the requirements for the instructions in a single word?

Answer 9

­ –cannot have dependencies
­ –cannot share resources
­ –only one memory access per word

Question 10

Read After Write (RAW)

Answer 10

True dependency

Question 11

Write After Write (WAW)

Answer 11

False dependency

Question 12

Write After Read (WAR)

Answer 12

False dependency

Question 13

3 Minimizing Dependencies Techniques

Answer 13

• -Branch prediction/ Sspeculation
• -Predication
• -Register Renaming

Question 14

Branch prediction

Answer 14

Predict which branch might be taken

Question 15

Predication

Answer 15

Use conditional moves

Question 16

Register Renaming

Answer 16

Used to avoid WAW and WAR dependencies