lERAN Flashcards
1
Q
Normally the first few bytes within a file, used to determine file type
A
file signature (windows)
1
Q
A whole number with a sign represented in 2’s complement format
A
signed Integer
2
Q
A file that contains a series of instructions a computer can perform
A
executable
3
Q
What Vulnerability occurs when a whole number is too large to be stored in the number of bits available?
A
Integer overflow
4
Q
How many bits is in ASCII? What does it contain?
A
7, Latin alphabet
5
Q
How many Bits is in extended ASCII?
A
8
6
Q
What is used for most web pages?
A
utf-8
7
Q
What is used for internationalization and localization of programs
A
utf-16
8
Q
Unicode is backwards compatible with ASCII T/F?
A
T
9
Q
An ____ is a sequence of discrete values i.e, 1s and 0s in a computer
A
Digital wave
10
Q
An _____ is a continuous sine wave with the potential for infinite resolution
A
analog wave
11
Q
What colors compose a pixel?
A
RGB
12
Q
What is Run-Length encoding (RLE) and what is it not effective at?
A
a compression technique that combines repeat values, bad with ascii plain text files
13
Q
What is lossless compression?
A
Saves image quality
14
Q
What is Lossy compression?
A
Saves image space
15
Q
What are file Extensions and what uses it?
A
bits that follow a file, windows use it
16
Q
What are File Signatures and what uses it?
A
The beginning bits of a file, Linux uses it
17
Q
What ASCII range contains (0-9)?
A
0x31-0x39
18
Q
What ASCII range contains lowercase alphabet
A
0x41-0x5a
19
Q
What ASCII range contains uppercase alphabet
A
0x61 - 0x7a
20
Q
What is the file extension/signature for Portable Document Format (PDF)?
A
.pdf, %pdf
21
Q
What is the file extension/signature for Rich Text Format?
A
.rtf \rtf
22
Q
What is the file extension/signature for MPEG Audio Layer-34?
A
.mp3, ID3
23
Q
What is the file extension/signature for Wave?
A
.wav, RIFF
24
What is the file extension/signature for Portable Graphics network (PNG)?
.png, .PNG
25
What is the file extension/signature for Bitmap Image
.bmp BM
26
What is the file extension/signature for Joint photographic Experts Group?
.jpeg JFIF
27
What is the file extension/signature for Audio Video Interleave?
.avi, AVI
28
What is the file extension/signature for Moving Picture Experts Group?
.mpeg ID3
29
What is the file extension/signature for Executable File Format?
.exe MZ
30
What is the file extension/signature for Executable and Linkable Format?
.elf .ELF
31
What is the file extension/signature for GZIP
.gz UA
32
What is the file extension/signature for ZIP
.zip PK
33
______ Is the use of electronic switches to solve Boolean functions and is fundamental to how computers are built
Digital Logic
34
_______ is an electronic device that performs a Boolean operation
logic gate
35
______ is a collection of logic gates configured to perform a particular function
digital circuit
36
The Vonn neuuuman architecture describes a ________ allowing instructions and data to be stored in memory rather then manually
store program concept
37
_____ are small amounts of storage space usually _________ in size
registers, 64 bits
38
_________ are used for any purpose and can be directly accessed by the programmer
General purpose registers
39
_______ are used for one single/special purpose and cannot be directly accessed by the programmer
Special purpose registers
40
_______ three digit GPR used by the arithmetic logic unit which executes arithmetic operations and logic decisions
Accumulator
41
_______ Two-digit SPR used to point the cu(control unit) to the correct memory address of the next instruction
Program Counter
42
_______ Three digit SPR used by the decoder to decode the instruction
Instruction Register
43
_______ Two-digit used to point to the correct memory address to read or write
memory address register
44
_______ Three digit SPR used to hold data to be read from or written to the ALU or memory, there are 100 memory locations, numbered 0-99
memory data register
45
_______ manages data passed from memory
Memory management unit
46
_______ performs fetch and decode steps by moving data and addresses between the registers and I/O or MMU
Control Unit
47
_______ Is the vocabulary or commands understood by the cpu and the interface that allows all software to run on hardware
ISA Instruction Set Architecture
48
What is an opcode?
numeric value that represents an instruction to the computer
49
What is an operand?
Indicates what data the operand is too work with
50
The process used by the cpu to retrieve, interpret, and perform each instruction of a program?
fetch decode execute
51
What is a mnemonic?
A sequence of characters to represent each opcode
52
HALT, mnemonic/opcode?
HLT 000
53
ADD, mnemonic/opcode?
ADD 1xx
54
Subtract, mnemonic/opcode?
SUB 2xx
55
Store, mnemonic/opcode?
STA 3xx
56
Load, mnemonic/opcode?
LDA 5xx
57
Branch unconditional, mnemonic/opcode?
BRA 6xx
58
Branch on zero, mnemonic/opcode?
BRZ 7xx
59
Branch on positive mnemonic/opcode?
BRP 8xx
60
Input, mnemonic/opcode?
INP 901
61
output, mnemonic/opcode?
OUT 902
62
PC > MAR >MDR >IR
HLT 000
63
A + MDR > A
ADD 1xx
64
A > MDR
STA 3xx
65
MDR > A
LDA 5xx
66
IR[ADDR] >PC
BRA 6xx
67
A - MDR > A
SUB 2xx
68
IF A === 0
BRZ 7xx
69
IF A >= 0
BRP 8xx
70
A ________ is a variable that holds more then one value
Buffer
71
A ________ occurs when to many variables are written too the buffer
buffer overflow
72
The goal of a ________ is to overwrite the function return address
stack overflow
73
What type of register set does CISC have and range of registers?
single register set 6-16
74
How many register operands per instruction?
one-two register operands per instruction
75
(CISC) parameter passing through _________
inefficient off-chip memory
76
CISC _______ - cycle instructions
multiple
77
CISC ________ length instructions
variable
78
CISC is good at pipelining T/F?
F
79
CISC Instructions are simple? T/F
F
80
CISC uses little edian?
T
81
Is CISC microprogrammed or hardwired?
microprogrammed
82
(CISC) complexity in _______
Microcode
83
CISC has many addressing modes T/F?
T
84
Many instructions can access memory.
T
85
_______ a computer architecture allowing several low level operations in one instruction
CISC
86
x86 is an example of _________ architecture
CISC
87
ARM is an example of ______ architecture
RISC
88
A computer architecture using only only one low-level operation
RISC
89
_______ stores data by the most significant bit
big edian (1234)
90
______ stores data by the least significant bit
little edian (4321)
91
CISC uses a ___________ architecture that supports data processing operations on both registers and memory locations
memory to register
92
RISC uses a ________architecture that supports data processing in registers only.
Load/store
93
What architecture uses fixed length?
RISC
94
What architecture is hard-wired?
RISC
95
What is TDP?
Thermal Dynamic Power
96
What is pipelining?
allows overlapping executions of multiple instructions in a single fetch-decode-execute
97
What is a superscalar processer?
uses a single fetch-decode-execute data path leading to multiple execute stages(must check for data dependecies)
98
What is instruction level parallelism?
each stage simultaneously having an instruction
99
What is multi-processing?
intelligent scheduling of instructions from two fetch-decode-execute paths, to a single execution stage
100
What does SISD stand for?
Single instruction, single data
101
What is Flynns Taxonamy?
Classify computers based on instruction/data
102
What does SIMD stand for?
Single instruction multiple data
103
What does MIMD stand for?
multiple instruction multiple data
104
What does MISD stand for?
Multiple instruction, single data
105
Is multi core processing true multi-tasking?
yes
106
What is an implementation of SIMD? A ____ is a memory structure that holds multiple values? _____
Short Vector Processing , vector
107
What is a TPM?
Trusted Platform Module, provides cyber security, bricks hard drives if tampered with
108
How do cpu's share data in a shared memory system?
Sharing a memory stick among themselves
109
How do cpu's share data in a distributed memory system?
The CPU's are cut out an independent segment of the memory stick and can only commuinicate using dedicated interconnect
110
What is a cluster
A group of pc's connected to eachother
111
What is symmetric multi-processing?
gives all processors equal access to the OS and all system resources
112
What is Asymmetric multi-processing?
one king CPU, the rest are subservient to the king
113
An integrated circuit configured by the customer using software is known as?
FAGL
114
Uses a mixture of floating point and integer arithmetic too get a base benchmark?
MIPS
115
______ creates a tailored benchmark
SPEC
116
A _____ is the connection between computer system components that move data
bus
117
What is the control signal that is sent if if a node fails to respond at an appropriate time?
heart beat
118
What is connected to the north bridge?
Video CPU Memory South Bridge
119
What is connected to the south bridge?
Hard disk, device interface, I/O module
120
What is represent by each line in a bus?
Address line
Data line
Control line
indicates the location data should be read/written from
transfers data
carries command signals
121
What computer architecture uses System on a chip and what is it?
RISC, processor, I/O ports, memory, GPU on a single chip
122
Buses communicate in different languages and speeds T/F?
T
123
I/o modules interface between the processor, memory, and one or more peripheral devices T/F?
T
124
A device interface is _________
the physical connector attaching peripheral devices to the computer
125
What are the three lines in a device interface mean?
Control
data
status
sends/recieves
holds data
bit recieve state
126
A _________ is the arrangement of the connections between computer system components
Bus topology
127
Multipoint bus connects ________
more than two peripheral devices
128
A point to point bus connects ________
only two components tpgeather
129
________ is a system for resolving bus control conflicts
Bus artribaition
130
What bus topology is connected in a series and gives the closest device priority?
Daisy chain
131
What bus topology request for buses are sent via directed control lines?
centralized parallel
132
What bus topology allows all devices to communicate bus requests too eachother?
Distributed using self-selcetion
133
The _______ is the method that the computer components use to transmit data between the sender and receives
bus protocol
134
serial communication ___________ relies on _________ (_________)
sends data one bit at a time, relies on handshaking for synchronizatrion
135
Parallel communication _______ relies on ___________ (_________)
sends a group of bits via multiple data lines, parallel communication relies on a clock signal for synchronization (synchronus)
136
____________ is a series of steps to coordinate asynchronous communication
Handshaking
137
The series of steps that handshaking goes through is as follows:
Step 1: Sync
Step 2: Syn/Ack
step 3: Ack
Data is synced up then acknowledged
138
__________ IEEEE-1284 _______ parallel communications
parallel port, point-point parallel communication
139
PATA _______ AKA integrated device electronics
multi=point parallel bus
140
________ RS-232 ___________
serial port, point to point serial communications
141
SAS ________ built on the small computer system interface (SCSI)
point to point serial bus built as successor to pata
142
PCIe an expansion bus uses channeled ________
point to point serial connections
143
USB ____________
point to point serial bus
144
type C (USBC) ________
fast reversible serial port
145
Lightning
porprietary assple device
146
Video Graphics Array
standard analog video interface for color resolution
147
Digital video interface
video interface designed for digital to digital connection
148
HDMI
High resolution multimedia
149
DisplayPort
can carry audio/video. Senhd digitized packets.
150
Memory mapped I/O control method is a scheme in which _____________
portions of ram are assigned to I/O devices
151
Programmed I/O (polling) is the process of _________
periodically checking I/O device status to determine a need for service
152
Programmed I/O
works well with ______
has the most ________
test the devices ______ before transferring each data byte
slow devices(keyboards)
overhead
status
153
What is interrupt driven I/O?
used to interrupt normal operation of a program executing on the cpu when a problem occurs
154
An _____ is an event typically triggered by an I/O device they are ______
Interrupt, asynchronus
155
An _______ is an event resulting from the execution of an instruction they are _________
exception, synchronus
156
_______ software invoked exceptions
Traps
157
______ occur when attempting division by zero when accessing memory incorrectly
Faults
158
_______ used to report software errors
Aborts
159
What range of intterupt/exception vector numbers are unmaskable/maskable?
0-31, 32-255
160
_______ is a process that provides a device controller with the ability to transfer data directly to or from memory without involving the processor
direct memory accesss
161
Direct memory access has low _______
Latency
162
Direct memory access has the ____________ but at the cost of hardware complexity
transfer rates
163
________ consists of the methods used to implement computer data storage
memory architecture
164
_______ is the time it takes memory to output set data
latency
165
________ is the act of storing data in a region of physical memory called
throughput
166
_____is the rate at which data is loaded from and stored to memory
buffering
167
What is a virtual memory address called?
Page
168
what is the principle of locality?
the same values, or related storage, are accessed frequently or sequentially
169
What is spatial/temporal locality?
data elements located near each other, referencing the same data often
170
what is the purpose of a translation lookaside buffer?
translates pages vm into frames physical memory
171
What is it called when a TLB/Cache contains/has already translated the data it was looking for? What is it called if it hasn't found it?
TLB/cache hit miss
172
what are the two types of mapping schemes?
directive, associative
173
What is a replacement policy?
If there is a cache miss, this makes room for the new data evicting an old block and turning it into a victim block
174
What does Least recently used (replacement policy method) do?
keeps a history of how often each cache block is used
175
What is first in, first out? (replacement policy method) do?
tracks the order in which blocks and place and gets rid of the first one in
176
what is random? (replacement policy method) do?
randomly evicts blocks providing a solution for thrashing
177
what is a write policy?
determines when to write data modified in cache back to ram
178
_______ updates cache and main memory ram
write-through
179
________ updates the block in main memory when the cache block becomes the victim block
write-back
180
what is a multi-level cache?
makes it so if there's a cache miss, it will Seach in a higher level of cache rather then going straight to ram
181
_______ allows for reading and writing data
RAM
182
________ each cell is made of 4-10 transfer d flop latch circuits(6t is most commen)
SRAM Static ram
183
___________ saves its stored data even if power is turned off
NVRAM Non-volatile ram
184
_______ is made of one transistor and one capacitor
dynamic ram dram
185
What is ROM?
Read only memory
186
______ programmed once for read only access during manufacture or by the customer using a special prom writer
Programmable Rom PROM
187
______ Erases data when ultraviolet light is applied
EPROM erassable Programmable ROM
188
______ can be erased and reprogrammed one byte at a time
EEPROM Electrical Erasable Programmable ROM
189
what is secondary memory?
secondary storage, non-volatile
190
how is data stored on a magnetic disk?
by leaving magnetic charges on a magnetized media surface
191
a ____ is a concentric circle on the platter
track
192
a combination of _____ across all platforms is called ________
tracks cyclinder
193
each ____ is given an address from the outside inward and is divided into ________
track, sector
194
What is the range of bytes a sector holds?
512-4096
195
disk platters spin ____ at a ______ measured in RPM
clockwise, constant linear velocity
196
Data transfer rates remains constant because the amount of sectors on each track does not change T/F?
T
197
______ Time required for the disc to reach operating rpm
spin-up time
198
_____ time it takes the head to move from current track to destination track
seek time
199
_______ time required for the desired sector of a track to rotate under the head
rotational latency
200
time needed to read/write to the data sector
transfer time
201
_______ time required to retrieve data from a storage device , the sum of spin-up time, seek time, rotational latency, and transfer time
disk access time
202
what addressing scheme does ssds use?
sata
203
_____ designed a smaller version of sata (ssds)
msata
204
______ ssd the size oif a stick of gum
m.2
205
_______ ssd used for high-end work stations/servers
u.2/u.3
206
_______ ssd enterprise used for data centers
E1/E3 edsff
207
What RAID level is used for performance but dosent allow disc failures?
RAID 0
208
What RAID level is primarily used for redundancys?
RAID 1
209
What RAID level is good at both redundancy and performance?
RAID 5
210
______ is a file server that connects to a network via ethernet
network attached storage
211
_____ are high speed, highly scalable usaully used by corporations for storage
storage area network
212
What is a distributed storage system?
The cloud
213
What are two examples of external memory?
Optical drive, magnetic tapes
214
in an optical discs operation the motor slows down as the laser moves from the inside edge to the outermost part of the disc T/F?
T
215
The optical disc spins clock-wise?
F
216
mov r0 #1 (operand addressing mode, type of architecture, what is it doing?)
immediate, ARM, overwriting r0 with the hex value of 1
217
move r0, r1 (operand addressing mode, type of architecture, what is it doing?)
register, register indirect memory, ARM, overwriting the contents of r1 into r0
218
ldr str r0, [r1] (operand addressing mode, type of architecture, what is it doing?)
register indirect memory, you read form left to right overwriting the contents of r0 by pointing the address at r1, ARM,
219
ldr r0, [r1, #16]! (operand addressing mode, type of architecture, what is it doing?)
pre-indexed memory, ARM, you start from the bang, adding 16 to register 1, you are then assigning the address of r1 to r0
220
ldr r0, [r1], #24 (operand addressing mode, type of architecture, what is it doing?)
post-indexed memory, ARM, adding 24 into the contents of register [r1] and then overwriting r0 with the contents of r1
221
ldr r1, [pc, #12]
pc relative ARM, adding 12 +8 because whenever you do pc relative you add 8, Coverting it into hex, adding that too the pc counter and then overwriting the contents of r1 with that new value
222
lsr r0, r1 #8
shift logical right, ARM, shifts the bits in r1 8 bits to the right, then puts the result in r0
223
lsl r0, r1, #4
shift logical left, ARM, shifts the bits in R1 two bits to the left and stores the result in R0
224
asr r0, r1, #2
arithmetic shift right, shifts the bit strings in R1 too the right retaining the sign(MSB) and stores the result in R0
225
ror r0, r1 #6
ARM rotate right, takes six bits from the right and stores them in the left like shift logical left, stores the result in 0
226
orr r0, r1, r2
ARM , OR checks if r1 or r2 are true or false if ones true then it returns a 1
227
bic r0, r1, r2
ARM bitclear, if the values are the same then there false, if they are false and the same then they are true, otherwise there true, then stored in r0
228
cmp
ARM compares two values if there equal it sets the zero flag in crispr
229
beq
ARM if the zero flag is set to 0, jumps too the label address in the operand
230
b
will jump to the label address regardless if flag is set to 0
231
push
sdecrements the sp by 4 then stores the value in the stack
232
pop
loads the value from the top of the stack adding 4 to the sp
233
bl
jumps to the function whos address is listed in the operand
