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cOMPUTER HARDWARE > lERAN > Flashcards

lERAN Flashcards

1
Q

Normally the first few bytes within a file, used to determine file type

A

file signature (windows)

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1
Q

A whole number with a sign represented in 2’s complement format

A

signed Integer

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2
Q

A file that contains a series of instructions a computer can perform

A

executable

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3
Q

What Vulnerability occurs when a whole number is too large to be stored in the number of bits available?

A

Integer overflow

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4
Q

How many bits is in ASCII? What does it contain?

A

7, Latin alphabet

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5
Q

How many Bits is in extended ASCII?

A

8

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6
Q

What is used for most web pages?

A

utf-8

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7
Q

What is used for internationalization and localization of programs

A

utf-16

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8
Q

Unicode is backwards compatible with ASCII T/F?

A

T

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9
Q

An ____ is a sequence of discrete values i.e, 1s and 0s in a computer

A

Digital wave

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10
Q

An _____ is a continuous sine wave with the potential for infinite resolution

A

analog wave

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11
Q

What colors compose a pixel?

A

RGB

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12
Q

What is Run-Length encoding (RLE) and what is it not effective at?

A

a compression technique that combines repeat values, bad with ascii plain text files

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13
Q

What is lossless compression?

A

Saves image quality

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14
Q

What is Lossy compression?

A

Saves image space

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15
Q

What are file Extensions and what uses it?

A

bits that follow a file, windows use it

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16
Q

What are File Signatures and what uses it?

A

The beginning bits of a file, Linux uses it

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17
Q

What ASCII range contains (0-9)?

A

0x31-0x39

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18
Q

What ASCII range contains lowercase alphabet

A

0x41-0x5a

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19
Q

What ASCII range contains uppercase alphabet

A

0x61 - 0x7a

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20
Q

What is the file extension/signature for Portable Document Format (PDF)?

A

.pdf, %pdf

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21
Q

What is the file extension/signature for Rich Text Format?

A

.rtf \rtf

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22
Q

What is the file extension/signature for MPEG Audio Layer-34?

A

.mp3, ID3

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23
Q

What is the file extension/signature for Wave?

A

.wav, RIFF

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24
Q

What is the file extension/signature for Portable Graphics network (PNG)?

A

.png, .PNG

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25
Q

What is the file extension/signature for Bitmap Image

A

.bmp BM

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26
Q

What is the file extension/signature for Joint photographic Experts Group?

A

.jpeg JFIF

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27
Q

What is the file extension/signature for Audio Video Interleave?

A

.avi, AVI

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28
Q

What is the file extension/signature for Moving Picture Experts Group?

A

.mpeg ID3

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29
Q

What is the file extension/signature for Executable File Format?

A

.exe MZ

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30
Q

What is the file extension/signature for Executable and Linkable Format?

A

.elf .ELF

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31
Q

What is the file extension/signature for GZIP

A

.gz UA

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32
Q

What is the file extension/signature for ZIP

A

.zip PK

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33
Q

______ Is the use of electronic switches to solve Boolean functions and is fundamental to how computers are built

A

Digital Logic

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34
Q

_______ is an electronic device that performs a Boolean operation

A

logic gate

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35
Q

______ is a collection of logic gates configured to perform a particular function

A

digital circuit

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36
Q

The Vonn neuuuman architecture describes a ________ allowing instructions and data to be stored in memory rather then manually

A

store program concept

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37
Q

_____ are small amounts of storage space usually _________ in size

A

registers, 64 bits

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38
Q

_________ are used for any purpose and can be directly accessed by the programmer

A

General purpose registers

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39
Q

_______ are used for one single/special purpose and cannot be directly accessed by the programmer

A

Special purpose registers

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40
Q

_______ three digit GPR used by the arithmetic logic unit which executes arithmetic operations and logic decisions

A

Accumulator

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41
Q

_______ Two-digit SPR used to point the cu(control unit) to the correct memory address of the next instruction

A

Program Counter

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42
Q

_______ Three digit SPR used by the decoder to decode the instruction

A

Instruction Register

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43
Q

_______ Two-digit used to point to the correct memory address to read or write

A

memory address register

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44
Q

_______ Three digit SPR used to hold data to be read from or written to the ALU or memory, there are 100 memory locations, numbered 0-99

A

memory data register

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45
Q

_______ manages data passed from memory

A

Memory management unit

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46
Q

_______ performs fetch and decode steps by moving data and addresses between the registers and I/O or MMU

A

Control Unit

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47
Q

_______ Is the vocabulary or commands understood by the cpu and the interface that allows all software to run on hardware

A

ISA Instruction Set Architecture

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48
Q

What is an opcode?

A

numeric value that represents an instruction to the computer

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49
Q

What is an operand?

A

Indicates what data the operand is too work with

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50
Q

The process used by the cpu to retrieve, interpret, and perform each instruction of a program?

A

fetch decode execute

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51
Q

What is a mnemonic?

A

A sequence of characters to represent each opcode

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52
Q

HALT, mnemonic/opcode?

A

HLT 000

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53
Q

ADD, mnemonic/opcode?

A

ADD 1xx

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54
Q

Subtract, mnemonic/opcode?

A

SUB 2xx

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55
Q

Store, mnemonic/opcode?

A

STA 3xx

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56
Q

Load, mnemonic/opcode?

A

LDA 5xx

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57
Q

Branch unconditional, mnemonic/opcode?

A

BRA 6xx

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58
Q

Branch on zero, mnemonic/opcode?

A

BRZ 7xx

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59
Q

Branch on positive mnemonic/opcode?

A

BRP 8xx

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60
Q

Input, mnemonic/opcode?

A

INP 901

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61
Q

output, mnemonic/opcode?

A

OUT 902

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62
Q

PC > MAR >MDR >IR

A

HLT 000

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63
Q

A + MDR > A

A

ADD 1xx

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64
Q

A > MDR

A

STA 3xx

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65
Q

MDR > A

A

LDA 5xx

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66
Q

IR[ADDR] >PC

A

BRA 6xx

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67
Q

A - MDR > A

A

SUB 2xx

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68
Q

IF A === 0

A

BRZ 7xx

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69
Q

IF A >= 0

A

BRP 8xx

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70
Q

A ________ is a variable that holds more then one value

A

Buffer

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71
Q

A ________ occurs when to many variables are written too the buffer

A

buffer overflow

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72
Q

The goal of a ________ is to overwrite the function return address

A

stack overflow

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73
Q

What type of register set does CISC have and range of registers?

A

single register set 6-16

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74
Q

How many register operands per instruction?

A

one-two register operands per instruction

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75
Q

(CISC) parameter passing through _________

A

inefficient off-chip memory

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76
Q

CISC _______ - cycle instructions

A

multiple

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77
Q

CISC ________ length instructions

A

variable

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78
Q

CISC is good at pipelining T/F?

A

F

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79
Q

CISC Instructions are simple? T/F

A

F

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80
Q

CISC uses little edian?

A

T

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81
Q

Is CISC microprogrammed or hardwired?

A

microprogrammed

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82
Q

(CISC) complexity in _______

A

Microcode

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83
Q

CISC has many addressing modes T/F?

A

T

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84
Q

Many instructions can access memory.

A

T

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85
Q

_______ a computer architecture allowing several low level operations in one instruction

A

CISC

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86
Q

x86 is an example of _________ architecture

A

CISC

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87
Q

ARM is an example of ______ architecture

A

RISC

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88
Q

A computer architecture using only only one low-level operation

A

RISC

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89
Q

_______ stores data by the most significant bit

A

big edian (1234)

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90
Q

______ stores data by the least significant bit

A

little edian (4321)

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91
Q

CISC uses a ___________ architecture that supports data processing operations on both registers and memory locations

A

memory to register

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92
Q

RISC uses a ________architecture that supports data processing in registers only.

A

Load/store

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93
Q

What architecture uses fixed length?

A

RISC

94
Q

What architecture is hard-wired?

A

RISC

95
Q

What is TDP?

A

Thermal Dynamic Power

96
Q

What is pipelining?

A

allows overlapping executions of multiple instructions in a single fetch-decode-execute

97
Q

What is a superscalar processer?

A

uses a single fetch-decode-execute data path leading to multiple execute stages(must check for data dependecies)

98
Q

What is instruction level parallelism?

A

each stage simultaneously having an instruction

99
Q

What is multi-processing?

A

intelligent scheduling of instructions from two fetch-decode-execute paths, to a single execution stage

100
Q

What does SISD stand for?

A

Single instruction, single data

101
Q

What is Flynns Taxonamy?

A

Classify computers based on instruction/data

102
Q

What does SIMD stand for?

A

Single instruction multiple data

103
Q

What does MIMD stand for?

A

multiple instruction multiple data

104
Q

What does MISD stand for?

A

Multiple instruction, single data

105
Q

Is multi core processing true multi-tasking?

A

yes

106
Q

What is an implementation of SIMD? A ____ is a memory structure that holds multiple values? _____

A

Short Vector Processing , vector

107
Q

What is a TPM?

A

Trusted Platform Module, provides cyber security, bricks hard drives if tampered with

108
Q

How do cpu’s share data in a shared memory system?

A

Sharing a memory stick among themselves

109
Q

How do cpu’s share data in a distributed memory system?

A

The CPU’s are cut out an independent segment of the memory stick and can only commuinicate using dedicated interconnect

110
Q

What is a cluster

A

A group of pc’s connected to eachother

111
Q

What is symmetric multi-processing?

A

gives all processors equal access to the OS and all system resources

112
Q

What is Asymmetric multi-processing?

A

one king CPU, the rest are subservient to the king

113
Q

An integrated circuit configured by the customer using software is known as?

A

FAGL

114
Q

Uses a mixture of floating point and integer arithmetic too get a base benchmark?

A

MIPS

115
Q

______ creates a tailored benchmark

A

SPEC

116
Q

A _____ is the connection between computer system components that move data

A

bus

117
Q

What is the control signal that is sent if if a node fails to respond at an appropriate time?

A

heart beat

118
Q

What is connected to the north bridge?

A

Video CPU Memory South Bridge

119
Q

What is connected to the south bridge?

A

Hard disk, device interface, I/O module

120
Q

What is represent by each line in a bus?

Address line
Data line
Control line

A

indicates the location data should be read/written from

transfers data

carries command signals

121
Q

What computer architecture uses System on a chip and what is it?

A

RISC, processor, I/O ports, memory, GPU on a single chip

122
Q

Buses communicate in different languages and speeds T/F?

A

T

123
Q

I/o modules interface between the processor, memory, and one or more peripheral devices T/F?

A

T

124
Q

A device interface is _________

A

the physical connector attaching peripheral devices to the computer

125
Q

What are the three lines in a device interface mean?

Control
data
status

A

sends/recieves
holds data
bit recieve state

126
Q

A _________ is the arrangement of the connections between computer system components

A

Bus topology

127
Q

Multipoint bus connects ________

A

more than two peripheral devices

128
Q

A point to point bus connects ________

A

only two components tpgeather

129
Q

________ is a system for resolving bus control conflicts

A

Bus artribaition

130
Q

What bus topology is connected in a series and gives the closest device priority?

A

Daisy chain

131
Q

What bus topology request for buses are sent via directed control lines?

A

centralized parallel

132
Q

What bus topology allows all devices to communicate bus requests too eachother?

A

Distributed using self-selcetion

133
Q

The _______ is the method that the computer components use to transmit data between the sender and receives

A

bus protocol

134
Q

serial communication ___________ relies on _________ (_________)

A

sends data one bit at a time, relies on handshaking for synchronizatrion

135
Q

Parallel communication _______ relies on ___________ (_________)

A

sends a group of bits via multiple data lines, parallel communication relies on a clock signal for synchronization (synchronus)

136
Q

____________ is a series of steps to coordinate asynchronous communication

A

Handshaking

137
Q

The series of steps that handshaking goes through is as follows:

Step 1: Sync
Step 2: Syn/Ack
step 3: Ack

A

Data is synced up then acknowledged

138
Q

__________ IEEEE-1284 _______ parallel communications

A

parallel port, point-point parallel communication

139
Q

PATA _______ AKA integrated device electronics

A

multi=point parallel bus

140
Q

________ RS-232 ___________

A

serial port, point to point serial communications

141
Q

SAS ________ built on the small computer system interface (SCSI)

A

point to point serial bus built as successor to pata

142
Q

PCIe an expansion bus uses channeled ________

A

point to point serial connections

143
Q

USB ____________

A

point to point serial bus

144
Q

type C (USBC) ________

A

fast reversible serial port

145
Q

Lightning

A

porprietary assple device

146
Q

Video Graphics Array

A

standard analog video interface for color resolution

147
Q

Digital video interface

A

video interface designed for digital to digital connection

148
Q

HDMI

A

High resolution multimedia

149
Q

DisplayPort

A

can carry audio/video. Senhd digitized packets.

150
Q

Memory mapped I/O control method is a scheme in which _____________

A

portions of ram are assigned to I/O devices

151
Q

Programmed I/O (polling) is the process of _________

A

periodically checking I/O device status to determine a need for service

152
Q

Programmed I/O
works well with ______
has the most ________
test the devices ______ before transferring each data byte

A

slow devices(keyboards)
overhead
status

153
Q

What is interrupt driven I/O?

A

used to interrupt normal operation of a program executing on the cpu when a problem occurs

154
Q

An _____ is an event typically triggered by an I/O device they are ______

A

Interrupt, asynchronus

155
Q

An _______ is an event resulting from the execution of an instruction they are _________

A

exception, synchronus

156
Q

_______ software invoked exceptions

A

Traps

157
Q

______ occur when attempting division by zero when accessing memory incorrectly

A

Faults

158
Q

_______ used to report software errors

A

Aborts

159
Q

What range of intterupt/exception vector numbers are unmaskable/maskable?

A

0-31, 32-255

160
Q

_______ is a process that provides a device controller with the ability to transfer data directly to or from memory without involving the processor

A

direct memory accesss

161
Q

Direct memory access has low _______

A

Latency

162
Q

Direct memory access has the ____________ but at the cost of hardware complexity

A

transfer rates

163
Q

________ consists of the methods used to implement computer data storage

A

memory architecture

164
Q

_______ is the time it takes memory to output set data

A

latency

165
Q

________ is the act of storing data in a region of physical memory called

A

throughput

166
Q

_____is the rate at which data is loaded from and stored to memory

A

buffering

167
Q

What is a virtual memory address called?

A

Page

168
Q

what is the principle of locality?

A

the same values, or related storage, are accessed frequently or sequentially

169
Q

What is spatial/temporal locality?

A

data elements located near each other, referencing the same data often

170
Q

what is the purpose of a translation lookaside buffer?

A

translates pages vm into frames physical memory

171
Q

What is it called when a TLB/Cache contains/has already translated the data it was looking for? What is it called if it hasn’t found it?

A

TLB/cache hit miss

172
Q

what are the two types of mapping schemes?

A

directive, associative

173
Q

What is a replacement policy?

A

If there is a cache miss, this makes room for the new data evicting an old block and turning it into a victim block

174
Q

What does Least recently used (replacement policy method) do?

A

keeps a history of how often each cache block is used

175
Q

What is first in, first out? (replacement policy method) do?

A

tracks the order in which blocks and place and gets rid of the first one in

176
Q

what is random? (replacement policy method) do?

A

randomly evicts blocks providing a solution for thrashing

177
Q

what is a write policy?

A

determines when to write data modified in cache back to ram

178
Q

_______ updates cache and main memory ram

A

write-through

179
Q

________ updates the block in main memory when the cache block becomes the victim block

A

write-back

180
Q

what is a multi-level cache?

A

makes it so if there’s a cache miss, it will Seach in a higher level of cache rather then going straight to ram

181
Q

_______ allows for reading and writing data

A

RAM

182
Q

________ each cell is made of 4-10 transfer d flop latch circuits(6t is most commen)

A

SRAM Static ram

183
Q

___________ saves its stored data even if power is turned off

A

NVRAM Non-volatile ram

184
Q

_______ is made of one transistor and one capacitor

A

dynamic ram dram

185
Q

What is ROM?

A

Read only memory

186
Q

______ programmed once for read only access during manufacture or by the customer using a special prom writer

A

Programmable Rom PROM

187
Q

______ Erases data when ultraviolet light is applied

A

EPROM erassable Programmable ROM

188
Q

______ can be erased and reprogrammed one byte at a time

A

EEPROM Electrical Erasable Programmable ROM

189
Q

what is secondary memory?

A

secondary storage, non-volatile

190
Q

how is data stored on a magnetic disk?

A

by leaving magnetic charges on a magnetized media surface

191
Q

a ____ is a concentric circle on the platter

A

track

192
Q

a combination of _____ across all platforms is called ________

A

tracks cyclinder

193
Q

each ____ is given an address from the outside inward and is divided into ________

A

track, sector

194
Q

What is the range of bytes a sector holds?

A

512-4096

195
Q

disk platters spin ____ at a ______ measured in RPM

A

clockwise, constant linear velocity

196
Q

Data transfer rates remains constant because the amount of sectors on each track does not change T/F?

A

T

197
Q

______ Time required for the disc to reach operating rpm

A

spin-up time

198
Q

_____ time it takes the head to move from current track to destination track

A

seek time

199
Q

_______ time required for the desired sector of a track to rotate under the head

A

rotational latency

200
Q

time needed to read/write to the data sector

A

transfer time

201
Q

_______ time required to retrieve data from a storage device , the sum of spin-up time, seek time, rotational latency, and transfer time

A

disk access time

202
Q

what addressing scheme does ssds use?

A

sata

203
Q

_____ designed a smaller version of sata (ssds)

A

msata

204
Q

______ ssd the size oif a stick of gum

A

m.2

205
Q

_______ ssd used for high-end work stations/servers

A

u.2/u.3

206
Q

_______ ssd enterprise used for data centers

A

E1/E3 edsff

207
Q

What RAID level is used for performance but dosent allow disc failures?

A

RAID 0

208
Q

What RAID level is primarily used for redundancys?

A

RAID 1

209
Q

What RAID level is good at both redundancy and performance?

A

RAID 5

210
Q

______ is a file server that connects to a network via ethernet

A

network attached storage

211
Q

_____ are high speed, highly scalable usaully used by corporations for storage

A

storage area network

212
Q

What is a distributed storage system?

A

The cloud

213
Q

What are two examples of external memory?

A

Optical drive, magnetic tapes

214
Q

in an optical discs operation the motor slows down as the laser moves from the inside edge to the outermost part of the disc T/F?

A

T

215
Q

The optical disc spins clock-wise?

A

F

216
Q

mov r0 #1 (operand addressing mode, type of architecture, what is it doing?)

A

immediate, ARM, overwriting r0 with the hex value of 1

217
Q

move r0, r1 (operand addressing mode, type of architecture, what is it doing?)

A

register, register indirect memory, ARM, overwriting the contents of r1 into r0

218
Q

ldr str r0, [r1] (operand addressing mode, type of architecture, what is it doing?)

A

register indirect memory, you read form left to right overwriting the contents of r0 by pointing the address at r1, ARM,

219
Q

ldr r0, [r1, #16]! (operand addressing mode, type of architecture, what is it doing?)

A

pre-indexed memory, ARM, you start from the bang, adding 16 to register 1, you are then assigning the address of r1 to r0

220
Q

ldr r0, [r1], #24 (operand addressing mode, type of architecture, what is it doing?)

A

post-indexed memory, ARM, adding 24 into the contents of register [r1] and then overwriting r0 with the contents of r1

221
Q

ldr r1, [pc, #12]

A

pc relative ARM, adding 12 +8 because whenever you do pc relative you add 8, Coverting it into hex, adding that too the pc counter and then overwriting the contents of r1 with that new value

222
Q

lsr r0, r1 #8

A

shift logical right, ARM, shifts the bits in r1 8 bits to the right, then puts the result in r0

223
Q

lsl r0, r1, #4

A

shift logical left, ARM, shifts the bits in R1 two bits to the left and stores the result in R0

224
Q

asr r0, r1, #2

A

arithmetic shift right, shifts the bit strings in R1 too the right retaining the sign(MSB) and stores the result in R0

225
Q

ror r0, r1 #6

A

ARM rotate right, takes six bits from the right and stores them in the left like shift logical left, stores the result in 0

226
Q

orr r0, r1, r2

A

ARM , OR checks if r1 or r2 are true or false if ones true then it returns a 1

227
Q

bic r0, r1, r2

A

ARM bitclear, if the values are the same then there false, if they are false and the same then they are true, otherwise there true, then stored in r0

228
Q

cmp

A

ARM compares two values if there equal it sets the zero flag in crispr

229
Q

beq

A

ARM if the zero flag is set to 0, jumps too the label address in the operand

230
Q

b

A

will jump to the label address regardless if flag is set to 0

231
Q

push

A

sdecrements the sp by 4 then stores the value in the stack

232
Q

pop

A

loads the value from the top of the stack adding 4 to the sp

233
Q

bl

A

jumps to the function whos address is listed in the operand

cOMPUTER HARDWARE (1 decks)

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