Lecture 4B: Modern CPU Hardware Architectures

Question 1

Define the term: Superscalar Processor.

Answer 1

A CPU that implements a form of parallelism called instruction-level parallelism within a single processor.

Question 2

A superscalar processor can execute more than one instruction during a ____ ____ by simultaneously dispatching multiple ________ to different ________ units on the processor.

Answer 2

A superscalar processor can execute more than one instruction during a [clock cycle] by simultaneously dispatching multiple [instructions] to different [execution units] on the processor

Question 3

What extra hardware is required to support Superscalar Processors?

Answer 3

Extra Functional Units are required to issue and execute multiple instructions in parallel.

Question 4

Define the term: Superpipelining.

Answer 4

A technique for improving the performance of a processor by splitting instructions into many separate “pipelines” that can be executed more or less in parallel.

Question 5

Superscalar Processors can execute only _______ instructions in parallel whereas _______ instructions are often _______.

Answer 5

Superscalar Processors can execute only [independent] instructions in parallel whereas [adjacent] instructions are often [dependent].

Question 6

Name the limitations of Superscalar Processors

Answer 6

Can only process independent instructions, require extra hardware.

Question 7

Define the term: Out-of-order execution.

Answer 7

Execute independent instructions in a different, more efficient order.

Question 8

What happens if a hazard causes stall cycles?

Answer 8

All instructions up to the offending instruction are stalled.

Question 9

What can help to prevent stall cycles?

Answer 9

Forwarding, branch prediction, and other techniques can reduce the number of stall cycles, but sometimes it is unavoidable.

Question 10

What are speculative instructions?

Answer 10

All execution within the instruction window is speculative (i.e., side-effects are not applied outside the CPU until it is committed.

Question 11

Advantages of Out-of-order execution.

Answer 11

Better performance.
> Exploit instruction-level parallelism (ILP)
> Hide latencies (e.g. L1 data cache miss, divide)

Question 12

Disadvantages of Out-of-order execution.

Answer 12

Hardware is much more complex, expensive, requires a larger chip area and has higher power consumption.

Question 13

Define the term: Dispatch. (out-of-order execution)

Answer 13

New instructions are added to the instruction window - reservation stations (RS)

Question 14

What happens in a Reservation Station? (out-of-order execution)

Answer 14

Instructions wait for their inputs. If instruction operands are ready they are sent to the FU. Otherwise, check on the bypass network and wait for operands.

Functional units (FU) > ALUs, AGUs, FPU

Question 15

What does a Bypass Network do? (out-of-order execution)

Answer 15

Broadcast computes values back to the reservation stations.

Question 16

What does a Reorder Buffer do? (out-of-order execution)

Answer 16

It allows instructions to be committed in order.

De-speculates execution, mostly by committing instructions in order.

Flushes the speculative instructions when a misprediction is discovered.

Question 17

What happens during the Commit process? (out-of-order execution)

Answer 17

• All execution within the instruction window is speculative (i.e., side-effects are not applied outside the CPU) until it is committed.
• Instructions can write to memory only when it is certain they should have been executed.
• Instructions must not affect the machine state while they are speculative.
• Instructions enter and leave the instruction window in program order, and instruction can only leave the window when it is the oldest instruction in the window and it has been completed.
• The instruction window is instantiated as RS & ROB.

Question 18

What is required in order for the Store Buffer dispatch a store? (Out-of-Order execution)

Answer 18

The store buffer dispatches a store only when the store has both it’s address and its data ready and there are no older stores awaiting dispatch.

Question 19

What are the features of a ‘Brainiac Design’ Processor?

Answer 19

Extra Hardware to achieve more Instruction Level Parallelism (ILP) out of code, millions of extra transistors, more design effort, consume more power.

Question 20

What are the features of a ‘Speed Demon’ Processor?

Answer 20

Run at higher clock speeds because they are simpler, have simple hardware design, have Less chip area, less power consumption.

Question 21

Define the term: ISA.

Answer 21

ISA provides commands to the processor, to tell it what to do, e.g., add, load, store.

Question 22

Define the term: CISC.

Answer 22

Complex instruction set computer (CISC)

Note: Complex instructions can execute several low-level operations such as load from memory, arithmetic, and a memory store.

Question 23

Define the term: RISC.

Answer 23

Reduced instruction set computer (RISC)

Note: Simple and 1 cycle instructions.

Question 24

What are the differences between RISC and CISC?

Answer 24

CISC:
• CISC puts emphasis on hardware.
• CISC was developed to make compiler development simpler.
• CISC is typically used for general-purpose computers.

RISC:
• RISC puts emphasis on software.
• RISC was developed to make hardware simpler.
• Typically used in smartphones.