Lecture 11: Multi-Core Processing Flashcards
What are our CPU Scheduling strategies for multi-core systems?
1) Asymmetric Multi-Processing
2) Symmetric Multi-Processing
List the components in Asymmetric Multi-Processing
1) 1 CPU = Master CPU (“Control Plan”)
2) Remaining CPU’s = Slave CPUs (“Data or Code Plane)
What does the Master CPU do and not do in Asymmetric Multi-Processing?
Does: All decisions with regards to:
1) Scheduling (Ready Queue to Running)
2) I/O Processing (from Running to I/O Queue)
3) System Activities
Doesn’t: Run actual code / processes themselves
What are the advantages of Asymmetric Multi-Processing?
1) No sharing: only one processor accesses the system data structures (Queues)
2) Good Load Balancing
List the components in Symmetric Multi-Processing
All CPUs = Master CPUs (no slave CPUs).
Describe the behaviour of Symmetric Multi-Processing:
1) Here, each processor is self-scheduling
2) All processors share a common ready queue or each processor may have its own private queue of ready processes
3) Whether there is a common ready queue or private ready queues, there is a scheduler for each processor that examines the ready queue and dispatches the CPU to a specific process for execution
What are the advantages or disadvantages of Asymmetric Multi-Processing?
Disadvantage: Sharing can cause issues –> each processor may update common queue or specific PCBs in queue
Advantage: Obvious performance increase - more CPUs in the multi-CPU system, we observe a directly proportional increase in system performance
What are the challenges for Multi-Processing Systems?
1) Processor Affinity
2) Load Balancing
Define: Processor Affinity
Process biasness towards a processor due to PCB information already being written into that particular CPU’s cache. (Reading/writing PCBs to caches is an expensive process and it is desirable to keep it minimized)
- higher the processor affinitiy, the lower load balancing we get
Define: Load Balancing
Evenly spread out CPU Utilization across all CPUs in the multi-processing system. Better load balancing = desirable
This applies to both systems: T or F: a process can move from the I/O queue back to the running state / processor
False; it always has to go through the Ready Queue to get back to a processor for processing
In Asymmetric Multi-Processing: T or F; All CPUs must communicate with each other
False; Only Master communicates with the Slaves
In Symmetric Multi-Processing: T or F; All CPUs must communicate with each other
True; otherwise they will lose their synchronization.
What happens to the cache when a process leaves the running state?
The contents of the cache memory must be invalidated due to the fact that the next time the process is scheduled, it may be scheduled to another processor
Is the contents of the cache memory being invalidated desirable?
Not really since read/write operations to memory (cache) are slow and, thus, not desirable. Thus, it would be better if the PCB info was allowed to stay in the cache and for the process to return to the same processor (this is processor affinity / process biasness)
