Lecture 08 - NEED TO FINISH Flashcards
Is MIPS a RISC or CISC ISA?
MIPS is a RISC iSA.
How many general purpose registers does MIPS 1 have?
32.
These are labeled r0-r31
How many floating point registers does MIPS 1 have?
32
Each are 32 bit.
How does MIPS 1 achieve double precision with floating point operations?
By using two single precision registers (one even and one odd).
Can MIPS do operations on memory without first storing the values in registers?
No.
MIPS is a load-store architecture. We can only use memory to load registers from memory and store registers to memory.
How many arguments do the following MIPS operations take?
add, sub, and, or
3.
Even floating point addition/subtraction have three arguments.
How many instruction formats does MIPS have?
What are they?
3:
R-type
I-type
J-type
What does an R-type MIPS instruction act on?
Registers
What is a J-type MIPS instruction used for?
Jumps
GO BACK THROUGH THE LAST SLIDE ON MIPS - IMMEDIATE AND INDEX MODE
GO DO IT NOW
What are the five stages of the MIPS fetch-execute cycle?
IF - Instruction Fetch ID - Instruction Decode EX - Execute (Do arithmetic etc.) MEM - Access memory if needed WB - Write back data to registers
How many stages is the MIPS pipeline?
MIPS has a 5-stage pipeline
Why can the fetch-execute cycle not be done in parallel for a single instruction?
Because each stage depends on the output of the last one.
Give three types of hazards that can cause a pipeline stall
- Structural Hazards
- Control Hazards
- Data Hazards
What is a structural hazard?
When two tasks can’t be completed because they both depend on the same hardware.
What is a data hazard?
When the input of one instruction depends on the output of another one.
What is a control hazard?
When a conditional branch changes which instructions should be executed.
Duplicating execution units is a possible solution to which type of pipelining hazard?
Structural Hazards.
Regarding Data Hazards and Pipelining, what is ‘Forwarding’?
When the ID hardware sets up a direct connection between ALU outputs and inputs so that the next instruction uses the correct value at the same time that it is written to the destination register.
In regards to Pipelining, why would Forwarding be preferred to Stalling?
Stalling wastes clock cycles idling, which means that instructions take longer, whereas forwarding does not extend the time it takes any instruction to go through the pipeline.
