Lec 2 - Storing bits with Flip Flops Flashcards

1
Q

How can a J-K Flop Flop be made to behave like a toggle (T Flip Flop)?

A

By setting both J and K to 1.

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2
Q

How can a J-K Flip Flop be made to behave like a D Flip Flop?

A

By setting J and K different, or setting both to 0.

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3
Q

Why is D Flip-Flop generally preferred over the R-S Flip Flop?

A

Because it is more stable and there is no illegal state of the output.

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4
Q

What is the role of the clock? How does it impact the changing state of Q and Q’?

A

The clock acts as a synchroniser for the inputs for the 2 NOR gates. As a result, changing the state of Q and Q’ are more stable as it requires the clock to be in its active state (1) to register input from the Pin.

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5
Q

Explain the behaviour of a D Flip Flop and how it is useful for digital circuit design.

A

Basically, the output (Q) will be equal to the input (Pin) only when the clock is in its active state (1). This is useful because it provides a function like the RS Flip-Flop while synchronising the inputs for 2 NOR gates, avoiding the racing condition.

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6
Q

Explain what happened when both inputs are set to 1 in a NOR gates RS Flip-Flop and why this is an issue for digital circuit design.

A

When both inputs are set to 1, both Q and Q’ are set to 0. This, however, is impossible since Q and Q’ are supposed to be different. This creates a racing condition for the circuit and should be avoided.

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7
Q

Describe behaviour of the RS Flip-Flop when one of the inputs is 1 (but not
both) and why this is useful for digital circuit design.

A

When one of the inputs is 1, it has an output (Q) of 0 or 1. This is useful for digital circuit design because it provides a simple switching function where a pulse (0 to 1) on the input (Set) sets the state of the circuit, and further pulsing on the input has no effect on the state until the Reset activates

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