Learning Guide Unit 4: Sequential Logic Flashcards
These cards will include information from all the reading assignment chapters.
What does implementing memory elements involve?
3 things. C, S, FL
Clocking, synchronization, and feedback loops.
What is a Flip-Flop? (Hint: Remembering) LLSGWMECBEI
A low-level sequential gate which memory elements can be embedded into.
How is the passage of time represented in most computers?
Hint: tick tock, Choo choo
It’s represented by a master clock that delivers a continuous train of alternating signals. Each clock cycle is modelled after one discrete time unit.
The data and the clock inputs enable the DFF to implement which time-based behavior formula?
Hint:it’s not out(t) =out(t-1)
out(t) = in(t - 1) where in and out are the gate’s input and output values and t is the current clock cycle.
What is a register?
Hint: porridge revise
Audi tee equals Audi tee subtracted fun
A storage device that can “store” a value over time by implementing the storage behavior out(t) = out(t-1)
What is the difference between a register and the DFF?
Hint: one can only show what it’s been given
The DFF can only output previous input, namely out(t) = in(t-1)
In a single-bit register, what does the small triangle represent?
It represents the clock input. This icon is used to state that the marked chip and the overall chip that encapsulates it is time-dependent.
The rules of chip design dictate that internal pins must have what?
A fan-in of 1, meaning they can be fed from a single source only.
Where did the term RAM derive from?
RAM - this term is derived from the requirement that read/write operations on a RAM should be able to access randomly chosen words, with no restriction on how they are accessed.
What are the two RAM design parameters?
Data Width - the width of each of its words.
Size - the number of words in the RAM.
What is a counter?
Hint:+1 each cycle
A sequential chip whose state is an integer number which increments every time unit, effecting the function out(t) = out(t-1) + c, where c is typically 1.
We allow sequential chips to be in “ “ during clock cycles, requiring only that at the beginning of the next cycle they output correct values.
unstable states
Define a sequential chip.
A chip that embeds one or more DFF gates, either directly or indirectly.
What is the hierarchy of sequential chips? Hint: There’s 4 of them.
- Data-flip-flops (DFF)
- Registers (based on DFFs)
- Memory banks (based on registers)
- Counter chips (also based on registers)
What does it mean when we say a DFF is “latched”?
Hint:changes and effect
It means that changes in their inputs have no immediate effect on their outputs
What is a single-bit register referred to as?
Hint:B.C.
A Bit, or binary cell
What 3 things does chip interface consist of?
Hint: I.P., L.P., O.P
- Input pin that carries a data bit
- A load pin that enables the cell for writes
- An output pin that emits the current state of the cell.
What is the read/write behavior of Bit and Register chips?
Hints: probing, asserting, register committed
Read: To read the contents of a register, we simply probe its output.
Write: To write a new data value d into a register, we put d in the in input and assert (set to 1) the load input. In the next clock cycle, the register commits to the new data value, and its output starts emitting d.
A w-bit counter consists of what two main elements?
Hint: WBR, CL
A regular w-bit register, and combinational logic.
A counter’s combinational logic is designed to do what?
Hint: 2 things (a and b: control bits)
a. compute the counting function
b. put the counter in the right operating mode, as mandated by the values of its three control bits.
An 8-register RAM is an array of what?
eight w-bit registers
What does a 64-register RAM consist of?
The ram ate eight of our eight chips.
An array of eight RAM8 chips
What does a w-bit register consist of?
Hint:aobc
An array of w binary cells.
Every logic gate-based memory device has an “ “ embedded in it
Hint: type of latch
S-R latch
What is a rising edge?
A transition from a low to a high signal. The symbol is an up arrow. ⬆
What is a falling edge?
A transition from a high to a low signal. The symbol is a down arrow ⬇
What does the S and R stand for in S-R Latch?
Set and Reset
The latch Sets Q and it can also Reset Q
D-Latch: These inputs allow the circuit to specify the data being stored in Q.
D (data input) and Clock
What kind of latch is this?
When a 0 is input to the Clock input of a D latch designed to capture data when the Clock equals 0, the latch appears to vanish, passing the signal D straight to Q.
The last value present on D when the Clock switches from 0 to 1 is stored on the output until Clock goes back to 0.
A transparent D latch
Chapter 10, section 10.3
What type of D latch can be used to divide a clock frequency in half?
Hint:ETDL
An edge-triggered D latch
Chapter 10, section 10.4
What did we use before USB ports were developed?
Hint:PP
A parallel port which had a 25-pin connector and was capable of sending/receiving 8-bits at a time to a printer or storage device.
Source: Chapter 10, section 10.6 Parallel Data Output
Aside from the data line, what other three additional lines are used to control memory transactions?
Hint: CS, RE, WE
Chip select, read enable, and write enable
An “ “ selects exactly one row of the memory array to
be active leaving the others inactive.
Hint: A. D.
address decoder
The processor uses the inputs “ “ and “ “ to
specify whether it is reading data from or writing data to the selected row of the memory array.
Hint: WE, RE
read enable and write enable
The system’s memory map should represent the full address range of the processor. This full address range is referred to as the processor’s what?
Hint: Montgomery Face
memory space
” “ is a method for using an address to enable a unique memory device while leaving all other devices idle.
Hint: A.D.
Address decoding
Chapter 12, section 12.3.3
What do all address schemes have in common?
Hint: Division
The bits of the full address are divided into two groups. One group that is used to identify the memory device and one group that identifies the memory location within the selected memory device.
