Learning Guide Unit 4: Sequential Logic

Question 1

What does implementing memory elements involve?
3 things. C, S, FL

Answer 1

Clocking, synchronization, and feedback loops.

Question 2

What is a Flip-Flop? (Hint: Remembering) LLSGWMECBEI

Answer 2

A low-level sequential gate which memory elements can be embedded into.

Question 3

How is the passage of time represented in most computers?
Hint: tick tock, Choo choo

Answer 3

It’s represented by a master clock that delivers a continuous train of alternating signals. Each clock cycle is modelled after one discrete time unit.

Question 4

The data and the clock inputs enable the DFF to implement which time-based behavior formula?
Hint:it’s not out(t) =out(t-1)

Answer 4

out(t) = in(t - 1) where in and out are the gate’s input and output values and t is the current clock cycle.

Question 5

What is a register?
Hint: porridge revise
Audi tee equals Audi tee subtracted fun

Answer 5

A storage device that can “store” a value over time by implementing the storage behavior out(t) = out(t-1)

Question 6

What is the difference between a register and the DFF?
Hint: one can only show what it’s been given

Answer 6

The DFF can only output previous input, namely out(t) = in(t-1)

Question 7

In a single-bit register, what does the small triangle represent?

Answer 7

It represents the clock input. This icon is used to state that the marked chip and the overall chip that encapsulates it is time-dependent.

Question 8

The rules of chip design dictate that internal pins must have what?

Answer 8

A fan-in of 1, meaning they can be fed from a single source only.

Question 9

Where did the term RAM derive from?

Answer 9

RAM - this term is derived from the requirement that read/write operations on a RAM should be able to access randomly chosen words, with no restriction on how they are accessed.

Question 10

What are the two RAM design parameters?

Answer 10

Data Width - the width of each of its words.
Size - the number of words in the RAM.

Question 11

What is a counter?
Hint:+1 each cycle

Answer 11

A sequential chip whose state is an integer number which increments every time unit, effecting the function out(t) = out(t-1) + c, where c is typically 1.

Question 12

We allow sequential chips to be in “ “ during clock cycles, requiring only that at the beginning of the next cycle they output correct values.

Answer 12

unstable states

Question 13

Define a sequential chip.

Answer 13

A chip that embeds one or more DFF gates, either directly or indirectly.

Question 14

What is the hierarchy of sequential chips? Hint: There’s 4 of them.

Answer 14

1. Data-flip-flops (DFF)
2. Registers (based on DFFs)
3. Memory banks (based on registers)
4. Counter chips (also based on registers)

Question 15

What does it mean when we say a DFF is “latched”?
Hint:changes and effect

Answer 15

It means that changes in their inputs have no immediate effect on their outputs

Question 16

What is a single-bit register referred to as?
Hint:B.C.

Answer 16

A Bit, or binary cell

Question 17

What 3 things does chip interface consist of?
Hint: I.P., L.P., O.P

Answer 17

1. Input pin that carries a data bit
2. A load pin that enables the cell for writes
3. An output pin that emits the current state of the cell.

Question 18

What is the read/write behavior of Bit and Register chips?
Hints: probing, asserting, register committed

Answer 18

Read: To read the contents of a register, we simply probe its output.
Write: To write a new data value d into a register, we put d in the in input and assert (set to 1) the load input. In the next clock cycle, the register commits to the new data value, and its output starts emitting d.

Question 19

A w-bit counter consists of what two main elements?
Hint: WBR, CL

Answer 19

A regular w-bit register, and combinational logic.

Question 20

A counter’s combinational logic is designed to do what?
Hint: 2 things (a and b: control bits)

Answer 20

a. compute the counting function
b. put the counter in the right operating mode, as mandated by the values of its three control bits.

Question 21

An 8-register RAM is an array of what?

Answer 21

eight w-bit registers

Question 22

What does a 64-register RAM consist of?
The ram ate eight of our eight chips.

Answer 22

An array of eight RAM8 chips

Question 23

What does a w-bit register consist of?
Hint:aobc

Answer 23

An array of w binary cells.

Question 24

Every logic gate-based memory device has an “ “ embedded in it
Hint: type of latch

Answer 24

S-R latch

Question 25

What is a rising edge?

Answer 25

A transition from a low to a high signal. The symbol is an up arrow. ⬆

Question 26

What is a falling edge?

Answer 26

A transition from a high to a low signal. The symbol is a down arrow ⬇

Question 27

What does the S and R stand for in S-R Latch?

Answer 27

Set and Reset
The latch Sets Q and it can also Reset Q

Question 28

D-Latch: These inputs allow the circuit to specify the data being stored in Q.

Answer 28

D (data input) and Clock

Question 29

What kind of latch is this?
When a 0 is input to the Clock input of a D latch designed to capture data when the Clock equals 0, the latch appears to vanish, passing the signal D straight to Q.
The last value present on D when the Clock switches from 0 to 1 is stored on the output until Clock goes back to 0.

Answer 29

A transparent D latch
Chapter 10, section 10.3

Question 30

What type of D latch can be used to divide a clock frequency in half?
Hint:ETDL

Answer 30

An edge-triggered D latch
Chapter 10, section 10.4

Question 31

What did we use before USB ports were developed?
Hint:PP

Answer 31

A parallel port which had a 25-pin connector and was capable of sending/receiving 8-bits at a time to a printer or storage device.
Source: Chapter 10, section 10.6 Parallel Data Output

Question 32

Aside from the data line, what other three additional lines are used to control memory transactions?
Hint: CS, RE, WE

Answer 32

Chip select, read enable, and write enable

Question 33

An “ “ selects exactly one row of the memory array to
be active leaving the others inactive.
Hint: A. D.

Answer 33

address decoder

Question 34

The processor uses the inputs “ “ and “ “ to
specify whether it is reading data from or writing data to the selected row of the memory array.
Hint: WE, RE

Answer 34

read enable and write enable

Question 35

The system’s memory map should represent the full address range of the processor. This full address range is referred to as the processor’s what?
Hint: Montgomery Face

Answer 35

memory space

Question 36

” “ is a method for using an address to enable a unique memory device while leaving all other devices idle.
Hint: A.D.

Answer 36

Address decoding
Chapter 12, section 12.3.3

Question 37

What do all address schemes have in common?
Hint: Division

Answer 37

The bits of the full address are divided into two groups. One group that is used to identify the memory device and one group that identifies the memory location within the selected memory device.