L8 - Memory Flashcards
What is the name of the memory internal to the processor?
Registers
How is external memory accessible by the processor?
Through IO modules
Cache is a form of ______ memory.
a) internal
b) external
a) internal
In what unit is memory capacity usually expressed
Bytes
What are the four methods of accessing units of data?
Sequential access
Direct access
Random access
Associative access
Define “associative access”
Word is retrieved based on a portion of its own contents rather than its address
Each location has its own address
Constant retrieval time
Cache memory may use associative
Information can be searched by type
***SPECIAL CASE OF RANDOM ACCESS***
Define “random access”
Each location has unique, wired in address
Any location can be selected and accessed
Access time is constant - same for any location
Order unimportant
Example: Main memory, cache
Define “direct access”
Shared read-write mechanism
Individual blocks have unique physical address
Access time depends on physical position of data
Example: Harddrive (R/W Mechanism is the magnetic head)
Define “sequential access”
Memory organized into units of data calld records
Access is made linearly, i.e. one record after another
Access time depends on position of required data
Example: Tape reel
What are the three performance parameters use with regard to memory?
Access time (latency)
Memory cycle time
Transfer rate
What is the access time (latency) of a memory system?
For random-access - time taken for a read/write operation
For non-random-access memory - time taken to position the read/write mechanism at desired location
Define “memory cycle time”
Access time plus any additional time before another access can commence
Example: time for R/W Head to move back to default position or time for SSD to calculate the address/difference etc.
Concerned with system bus, not processor
Define “transfer rate” as it applies to memory systems.
Rate at which data can be transferred into or out of a memory unit
For random access memory, 1/(cycle time)
What is memory hierarchy?
Balance of cost, speed and capacity
In general, increased speed = increased cost & decreased capacity
increased capacity = decreased speed & increased price
etc.
So for a good balance can use many different memory components
Describe the process of reading from memory
1) Source address put in Memory Address Register
2) Address bus set to value of MAR
3) Control line set to “read”
4) Data bus set to value at address in MAR
5) Memory buffer register set to value of Data bus