introduction to 80386

Question 1

80386 processor types:

Answer 1

1. SX : 24 bit address bus and 16 bit data bus.
2. DX : 32 bit address bus and data bus.

its campatible with 8086,8088,80186,80286,80188 chips.

Question 2

memory feature of 80386 DX

Answer 2

4 GB physical mem, 64 TB virtual mem.

Question 3

Speed?

Answer 3

20 MHz instructions.

Question 4

pipelined:

Answer 4

Simultaneous instruction featching, decoding, execution and memory management.

Question 5

Features of 80386DX architecture:

hint : what helps to shorten instruction execution time.

Answer 5

3 stage pipeline.
fetch-decode-execute
Pipelined architecture. Instruction pipelining, a high bus bandwidth, on-chip address translation significantly shortens the average instruction execution time.

3 to 4 million instructions per second.

Question 6

data types supported:

Answer 6

17

Question 7

Modes in 80386DX:

and about modes.

Answer 7

Built in virtual memory management circuitry and protection circuitry required to operate an 80386DX in these modes.

can operate in real mode: as fast as 8086 or real mode 80286.
protected mode: provides paging, virtual addressing, multilevel protection and multitasking and debugging.

virtual mode.

Question 8

808386DX architecture: overall….

Answer 8

3 sections :

a. CPU
1. Execution Unit
i. Control Unit
ii. Data unit
iii. Protection Test Unit.
2. Instruction decode unit.
b. Memory management unit.
1. Segmentation
2. Paging
c. Bus Control unit.

Question 9

Pipelined Instructions processing:

Answer 9

fetching, decoding, execution, memory management and bus accesses for several instructions are performed simultaneously.

Question 10

what does execution unit do?

Answer 10

Fetch data from instruction q and executes it.

Question 11

Microcode:

Answer 11

Processor design technique that interposes a layer of computer organisation between the CPU hardware and the programmer visible instruction set architecture of comp.

Question 12

Control Unit:

Answer 12

Has microcode and special hardware.
Speeds effective address calculation.
Quick multiply and divide.

Question 13

Data Unit :

Answer 13

64 bit barrel shifter (shift multiple bit in once clock)
Contains ALU,
Eight 32 bit general purpose registers.

Fast shift and rotate operations so fast multiply and divide.

Question 14

Protection Test Unit:

Answer 14

Detects segmentation violations.

Question 15

Instruction Decode Unit:

Answer 15

takes instruction bytes from prefetch Q and translates into microcode.
Decoded info is stored in instruction Q. passed to control section.

Question 16

Segmentation Unit :
what does it do? how does it do?

what about protection mech?

Answer 16

• Translates logical address into linear address at request on execution unit.
• b4 calculating, it checks access rights.
• 4 level Protection mechanism to isolate system code and data from app prog.
• adds segment base and effective address to generate linear address.

Question 17

Address translation:

Answer 17

Logical to linear to physical.

Segmentatn | Paging

Question 18

Paging Unit :

does what and for whom?

Answer 18

-Translates linear add to physical address.
- Gives physical add to Bus Interface Unit to perform memory and I/O access.
organizes add in terms of pages of 4kb size each.

PLA’s check privileges and avoid invalid access.

Question 19

PLA :

Answer 19

A programmable logic array (PLA) is a kind of programmable logic device used to implement combinational logic circuits. The PLA has a set of programmable AND gate planes, which link to a set of programmable OR gate planes, which can then be conditionally complemented to produce an output. It has 2N AND gates for N input variables, and for M outputs from PLA, there should be M OR gates, each with programmable inputs from all of the AND gates. This layout allows for many logic functions to be synthesized in the sum of products canonical forms.

PLAs : both the AND and OR gate planes are programmable.

Application:
PLA is used to provide control over datapath.
PLA is used as a counter.
PLA is used as a decoder.
PLA is used as a BUS interface in programmed I/O.

Question 20

Bus Control Unit :

provides what?
responsible for what?

Answer 20

• 32 bit bideirectional data bus.
  32 bit address bus.
• Accepts internal requests for code fetch, for data transfers from code fetch and execution unit.
  prioritizes req, generates signals to perform bus cycles.
• Sends address, data and control signals to communicate w memory and IO.

address driver drives : bus enable and address signal A0 to A32.

• address relocation
• control interface bus masters and coprocessors.

Question 21

Instruction Prefetch Unit :

Answer 21

fetches sequentially the instruction byte stram from memory.
uses bus control unit for tht, when bus is not executing.

these prefetched instuc stored in 16 byte code Q.
fetches in order, 1 double word at a time.

Question 22

Instruction precode unit:

Answer 22

Takes instruction bytes from the instruction prefetch Q and translates them into microcode. this is then stores in Instruction Q.