Introduction

Question 1

Difference between Testing and Design Verification.

Answer 1

Testing: Detect fabrication defects and faults that appear during operation.
Verification Detect erros introduced in the design phase.

Question 2

Which is the “stuck at fault” problem formulation?

Answer 2

Given a combinational circuit and a stuck at fault, determine a set of assignmets at the inputs (test pattern) such that the faulty-free and faulty circuit produce different outputs.

Question 3

Which are the 3 basic approachs to design verification?

Answer 3

Simulation:
Stimuli are chosen to show a certain behaviour, or they are generated randomly.

Emulation: Construction of a prototype (e.g. using FPGA).

Formal Verification:
Application of exact mathematical proof methods (performed by software) to check circuit properties.

Question 4

Motivation for formal verification (5 reasons).

Answer 4

• Important for safety critical systems
• Increasing complexity of SoC designs (simulation not always provide cover).
• IP core based designs (it has to function in different circuits).
• Better trade off between productivity and quality.
• High portion of the design spent on verification.

Question 5

Why can simulation fail?

Answer 5

Due to logic structures, some internal circuit nodes are difficult to stimulate using random patterns (“random pattern resistant”).

Circuits with large sequencial depth (couter).

Question 6

Question to be responded by design verification.

Answer 6

Does the formal description(RTL) of design fullfil the expectations of the designer (informal verification)?

• Can unexpected things occur? (Deadlock)
• Do certain things always work?
• Are there unexpected side effects?

Method: formal: property checking
informal: simulation.

Question 7

Question to be responded by Implementation Verification.

Answer 7

Is the formal specification (e.g. at RT-Level) translated correctly into the implementation (e.g. at gate level)?
Sources of errors:
-Bugs in the tool.
-problems with interfacing of tools
 -manual interaction of designers 

Method/tool, formal: “equivalence checking“
non-formal: simulation (almost disappeared)

Question 8

Can simulation be used in formal verification?

Answer 8

Yes, simulate all possible inputs and sequence of inputs.