Intro Flashcards
T F
All Boolean logic expressions can be rewritten in terms of only NAND instructions.
True.
The nand function is universal, which means that every Boolean operator can be written in terms of nands. For example, (notA) has the same truth table as ( A nand A). Similarly, (A and B) can be written as (not (A nand B). The final expression, while ugly is
((Anand B) nand (A nand B) ) which has the same truth table as the original expression.
T F
Speedup is the ratio of new execution time to old execution time. Note: Remember, the term ratio of A to B always means A/B
False
It’s old execution time divided by new execution time, which is equivalent to new performance divided by old performance.
T F
The Clock Rate (CR) for a given CPU has units of seconds per tick.
False
Clock Rate has units of cycles or ticks per second.
Clock Cycle Time has units of seconds per tick.
T F
Computers used as servers are likely to have more cache levels than those intended for mobile or hand-held devices.
True
Go visit the diagram at the beginning of Chapter 2 of the 5th edition of Hen- nessey and Patterson that shows typical CPU/Memory configurations for servers and mobile machines. Typical applications of Mobile/hand-held devices consist of many transactions on small amounts of information—not massive information throughput. Conversely, server operations are dominated by bulk information transfer–both data and instructions. A typical transaction would require delivery of a few very large blocks. So, using a third level of cache would increase the amount of information which could be accessed without a vist to RAM. This actually exploits spatial locality.
T F
The execution time of a program on a machine with a clock cycle time of one nanosecond will likely decrease when the clock is replaced by one with a five nanosecond clock cycle time.
False
Clock Rate has units of cycles or ticks per second. Clock Cycle Time has units of seconds per tick.
T F
The MIPS rating of a computer is an excellent metric to compare the performance of two general purpose computers.
False
Not all instructions on general purpose computers take the same amount of time. It is not reasonable to assume that the expected value (average) of the time to execute a million arbitrary instructions on any CPU will be one second. While there may, indeed, be some set of a million instructions which will execute in a second, there is no guarantee that the associated programs will do any real work at all. In a set of programs dominated by floating point instructions, MIPS will be overly optimistic.
If we write the MIPS rating in terms of the CPU execution time equation, we get
MIPS = IC/CPU Time x 10^6 = CR/CPI x 10^6
So, as expected, the MIPS rating for a given machine depends on the set of instructions. Hopefully, you now understand why CPU performance comparisons require the context of relevant benchmarking programs to be meaningful.
A similar argument can be made for the MFLOPS rating, which will be overly pessimistic for sets of programs dominated by integer ALU instructions.
For more information regarding comparisons of arithmetic operationexecution times on two CPU’s
stackoverflow.com/questions/2550281/floating-point-vs-integer-calculations-on-modern-hardware
T F
RAM allows the information at any address to be read or written directly. In contract, ROM access is sequential.
False
ROM supports random access by address, just like RAM.
Sequential access means that traversing all the addresses between either the smallest address and the target address or the current address and the target address. Tape is one of the technologies which supports only sequential access.
T F
Writing a specific address in ROM requires traversing all the addresses between either the smallest address and the target address or the current address and the target address.
False
ROM cannot be written - only read.
ROM supports random access by address, it’s not sequential.
T F
A machine with Big Endian memory organization will always put the least significant byte of a 4-byte long 2’s complement integer at address B=3 mod 4.
True
In a Big Endian memory organization, the address of the MSB (most significant byte) of a multi-byte object is at an address C, where C = 0 mod 4. The LSB (least significant byte) of a multi-byte object is at B, the largest address in byte-addressable memory associated with that object, where B = 3 mod 4
T F
The average number of instructions (IC) in a set of programs is independent of the number of clocks per instruction (CPI).
False
The IC and CPI both depend on the ISA (instruction set architecture).
For example, in a RISC machine, a complex instruction from a CISC machine may need to be converted to several simpler instructions, thus increasing the IC. By definition, RISC machines don’t support many of the complex CISC instructions; so the CPI is expected to decrease.
T F
The average CPU execution time is independent of time required to produce the executable image of a program.
True
The executable image is generated prior to runtime. Time required to produce the executable has no impact on the average CPU execution time.
T F
A C program will always run faster on a computer with a 1.2GHz clock than one with a 500MHz clock.
False
A faster clock does not necessarily make all programs faster. For example, programs that are memory bound or have human-driven I/O do not depend on the clock for their speed.
T F
The execution time of the average program running on a given computer architecture can usually be improved by decreasing the clock rate.
False
Decreasing the clock rate is the same as decreasing the number of ticks per second (or whatever time unit you have). That means that the machine does less work each second; so, execution time is not likely to improve.
T F
In a Abigail Endian machine, the lsb (least significant bit) of a 64 bit register is the right-most bit.
False
Endian-ness is about memory address, not about registers, and not about left or right.
T F
A machine with the highest MFLOPs rating available would be a good choice for a warehouse system providing cloud services.
False
Cloud computing involves supporting remote users in accessing their data and services. It is unlikely that floating point computations will dominate. So, MFLOPs will probably be overly pessimistic.
T F
An enhancement of machine A is desirable when the ration of the average performance of the enhanced manchineel (E) to the average performance of the original or native machine A is less than one (1).
False
If the ratio of performance on E to performance on A (E divided by A) is less than one, then the number of jobs per time on the native machine (A) was larger than the number of jobs per time on the supposedly enhanced machine E, meaning the enhancement degraded the performance.
T F
The sign bit of a double precision floating point number in a byte-addressable Big Endian architecture is stored in the byte at address P, where P = 7 mod 8
False
In a Big Endian memory organization, the sign bit is in the MSB which is at an address which is 0 mod 8.
T F
Adding a new type of ALU instruction to a computer’s Instruction Set Architecture has no effect upon the CPI (number of clocks per instruction).
False
See worksheet one or the problem in the 2nd part of the exam where we create a new ALU2 instruction which contains an opera do that is nw used again. Or, look at the relationship between the average CPI and the enumerated types of instructions: ALU, Load, Store, Control vs INT ALU, FP ALU, Load, Store, Control
T F
An instruction which loads a single byte of data from an address that is 0 mod 1 will never produce a byte alignment error as long as memory is byte addressable.
True
That’s what is means to be byte addressable. This question is here so I can tell you that there is no way to get the least significant 4-bits (nybble) and the most significant 4 bits from two consecutive words in memory without loading both bytes and then concatenating the appropriate parts.
T F
Decreasing the average instruction count for a given machine will improve the execution time of all programs run on that machine.
False
Decreasing the average IC does not mean that the CPI decreases for all instructions. So, it is possible that the execution time of some programs will not change because it uses no instructions for which the IC changed. Another reason it’s false is because if a program is I/O bound or memory bound - meaning that memory delays or waiting for slow inputs or outputting to a slow device dominates the execution time, then the impact of a change in the CPI may be negligible.
T F
The information on an EPROM can be modified by removing the chip from the machine, applying a special voltage that erases the last values burned in, then burning in new information and returning the updated chip to the machine.
False
An EPROM is an erasable programmable ROM which is erased by applying ultraviolet light to the small window on top of the chip. The original statement applies to EEPROM, which is electrically erasable programmable ROM. Flash memory was produced by modifying the EEPROM technology to allow updates without removing the chip from the machine.
T F
The instruction count of s program is independent of the method of implementing the instructions, of choosing which instructions to execute, and of the number of instructions used in the program.
False
The clock cycle time change is independent of the method of implementing the instructions, of choosing which instructions to execute, and of the number of instructions used in the program.
T F
On a byte aligned machine, an instruction that loads an 8 byte object must be stored at an address that is. 0 mod 8.
False The ISA (instructions set architecture)is what determines how long an instruction must be. IA32 used in the X86 family of machines -those lovely intel guys, has instruction lengths between 1 byte and 5 bytes. Conversely, MIPS instructions are all 4-bytes long. It is the 8 byte word which must have an address that is 9 mod 8 in a byte-aligned machine.
T F
A computer modification that changes the average number of clock cycles per instruction will never cause the instruction count to change.
False
If the modification causes the average number of clock cycles to decrease by removing all the complex instructions, then the instruction count is likely to increase when each instantiation of a single complex instruction is replaced by the equivalent sequence of simpler instructions. This is why pipelining was required to make RISC architectures dominate the computer market - the exploitation of instruction level parallelism was necessary to handle more instructions in less time.
