Intro Flashcards
What are the front end steps?
- Design Specification
- RTL coding
- Functional Simulation
- Coverage Analysis
What are the synthesis steps according to RAK?
- Logic mapping (synthesis)
- DFT synthesis
- ATPG vector generation
What are the physical steps according to RAK?
- Floor planning
- Power planning
- Placement
- CTS
- Routing
What is final validation according to RAK?
- STA
- GLS
What is a design specification?
A Design Specification is an explicit set of requirements to be satisfied by a material, product or service.
What is a HDL
An HDL is a description language with special constructs for modeling hardware concurrency and timing.
What are the levels of abstraction for HDL?
Behavioral, Structural, Time Model
benefits of HDL
Increased productivity due to higher level of abstraction, in ascii, enables design reuse, description is independent of implementation
What is the Cadence RTL simulator?
Xcelium,
started with:
xrun <source></source> [options] -top [lib.]cell[.view]
What are the major steps of a Xcelium run?
- Compilation, create design data objects
- Elaboration
- Execute simulation code
Xcelium compile only
xrun -compile <files></files>
What is the Cadence Verilog Debugger
SimVision which is part of Verisium Debug
How to invoke SimVision?
xrun <source></source> -access +rwc -gui
How to invoke the coverage tool
make sure you start xrun with -coverage all
What is CCS and NLDM
CCS = Composite Current Source
NLDM = Non Linear Delay Model
What is a timing model?
A timing model consists of driver model, net model and a receiver model. Driver model and receiver models are typically characterized using a circuit simulator, whereas net model is either estimated (wire-load, manhattan or star topology) or extracted from a layout using technology parameters of metal, via and contact etc.
What is the NLDM driver model?
NLDM driver model characterizes input-to-output delay and output transition times with sensitivity to input transition time, output load and side input states.
