Interconnects Flashcards
What are interconnects?
Components used to connect 2 or more components
What are 4 important concepts within generic interconnects?
Topology
Routing
Arbitration
Switching
What does SoC mean?
System on Chip
What is AMBA?
Introduced by ARM
Open standard, on-chip interconnect
Used to connect CPU cores within a processor, and peripherals in a SoC
What are peripherals?
Any external device (USB, PSIs)
What is the APB and why is it efficient to use instead of the main bus?
Advanced Peripheral Bus
Connects to the low-bandwidth peripherals. When we have more niche peripherals, which we don’t need to connect to that often, these don’t have to be at the main interconnect (UART, SPI, I²C).
If all of these was put on the main interconnect, the design could potentially take more space and become more convoluted (complex). Could cause congestion.
What does it Single-master mean when taking about APBs?
The APB is what we call a single master, i.e. the AHB.APB bridge
What is the main use of APB?
Reading and writing registers.
Writing data is often a way of controlling peripherals.
What is the AHB-to-APB bridge used?
AHB: High performance
APB: Low performance, working on a frequency much lower than the core. Would be very inefficient to be connected via the main interconnect.
What is the AHB?
Advanced High-Performance Bus
What components does the arbitration process consist of?
Contains:
Arbiter: controls access
One unidirectional address buss (HADDR)
Two unidirectional data buses (HWDATA, HRDATA), allows us to transfer the data back and forth between the systems.
Only one data bus is active at the time, can either write or read
What is HWDATA and HRDATA in the AHB arbiter?
Hardware write data
Hardware read data
Describe AHB arbitration
The main requests the bus
The arbiter grants one main the bus
The arbiter protocol is not defined by specification, but the implementation.
Name some examples of an arbitration protocol
Round robin (can be inefficient)
Prioritization
How does AHB address decoding work?
Each slave has its own memory region
Because of this, based on the address, the decoder knows which slave to select
How does the simple data transfer protocol in AHB work?
Main requests the bus, and output address (HADDR) and type of access (control) are what the main is requesting
- e.g.: I want “this” address, and I want to write to it
Once it has been granted, the data transfer happens in the next cycle
How does the AHB basic transfer work?
When communicating between a main and a side
Main waits until the side signals that it is ready (HREADY)
How can AHB be pipelined?
Within the interconnects there are very few irregularities. You are not gonna have a data transfer fail, at least this can assumed.
Because we have an address phase and a data phase, these can be running in parallel.
Pipelining increases bus bandwidth.
What are burst transfers?
When transferring more than one unit.
signal: HBURST - says how much we are actually sending
Signal to side that multiple data transfers will occur.
Enables optimisations and buffering
What was the original AHB architecture?
Single access:
- single address mux
- single read mux
- single write mux
What does a multilayer AHB architecture look like?
One mux per main/side
Requires an arbiter for each side
Support for parallel accesses, when mains access different sides
Requires more wires
Describe the AMBA 3.0 protocol
Separates the transactions: read addr, write addr, read data, write data and write response channels
OoO transaction completion
Enhanced protection support: Secure/non-secure transaction specification. Ensures that in more volatile situations critical operations are successful
Fixed mode burst support
Advanced system cache support: specify if transaction is cacheable/bufferable. Specify attributes (such as write-back/write-through)
Exclusive access (for semaphore operations)
Can do register slice support for high frequency operation
Name a difference between AHB and AXI Burst
AHB:
- address and data are locked together
- have to specify address within each cycle because the side is not doing any address calculation
AXI:
- address calculation is delegated to the side
- the side automatically calculates the steps of the transfer
- the data access has to be sequential address wise
- this frees up the address port on the main
- can do simultaneous read and write transactions
How does OoO completion differ between AHB and AXI?
AHB:
- if one side is slow, all data is held up
- SPLIT transactions provide very limited improvement
AXI:
- Multiple outstanding addresses, OoO completion allowed
- Fast sides may return data ahead of slow sides
