Interconnects

Question 1

What are interconnects?

Answer 1

Components used to connect 2 or more components

Question 2

What are 4 important concepts within generic interconnects?

Answer 2

Topology

Routing

Arbitration

Switching

Question 3

What does SoC mean?

Answer 3

System on Chip

Question 4

What is AMBA?

Answer 4

Introduced by ARM

Open standard, on-chip interconnect

Used to connect CPU cores within a processor, and peripherals in a SoC

Question 5

What are peripherals?

Answer 5

Any external device (USB, PSIs)

Question 6

What is the APB and why is it efficient to use instead of the main bus?

Answer 6

Advanced Peripheral Bus

Connects to the low-bandwidth peripherals. When we have more niche peripherals, which we don’t need to connect to that often, these don’t have to be at the main interconnect (UART, SPI, I²C).

If all of these was put on the main interconnect, the design could potentially take more space and become more convoluted (complex). Could cause congestion.

Question 7

What does it Single-master mean when taking about APBs?

Answer 7

The APB is what we call a single master, i.e. the AHB.APB bridge

Question 8

What is the main use of APB?

Answer 8

Reading and writing registers.
Writing data is often a way of controlling peripherals.

Question 9

What is the AHB-to-APB bridge used?

Answer 9

AHB: High performance

APB: Low performance, working on a frequency much lower than the core. Would be very inefficient to be connected via the main interconnect.

Question 10

What is the AHB?

Answer 10

Advanced High-Performance Bus

Question 11

What components does the arbitration process consist of?

Answer 11

Contains:

Arbiter: controls access

One unidirectional address buss (HADDR)

Two unidirectional data buses (HWDATA, HRDATA), allows us to transfer the data back and forth between the systems.

Only one data bus is active at the time, can either write or read

Question 12

What is HWDATA and HRDATA in the AHB arbiter?

Answer 12

Hardware write data

Hardware read data

Question 13

Describe AHB arbitration

Answer 13

The main requests the bus

The arbiter grants one main the bus

The arbiter protocol is not defined by specification, but the implementation.

Question 14

Name some examples of an arbitration protocol

Answer 14

Round robin (can be inefficient)

Prioritization

Question 15

How does AHB address decoding work?

Answer 15

Each slave has its own memory region

Because of this, based on the address, the decoder knows which slave to select

Question 16

How does the simple data transfer protocol in AHB work?

Answer 16

Main requests the bus, and output address (HADDR) and type of access (control) are what the main is requesting
- e.g.: I want “this” address, and I want to write to it

Once it has been granted, the data transfer happens in the next cycle

Question 17

How does the AHB basic transfer work?

Answer 17

When communicating between a main and a side

Main waits until the side signals that it is ready (HREADY)

Question 18

How can AHB be pipelined?

Answer 18

Within the interconnects there are very few irregularities. You are not gonna have a data transfer fail, at least this can assumed.

Because we have an address phase and a data phase, these can be running in parallel.

Pipelining increases bus bandwidth.

Question 19

What are burst transfers?

Answer 19

When transferring more than one unit.

signal: HBURST - says how much we are actually sending

Signal to side that multiple data transfers will occur.

Enables optimisations and buffering

Question 20

What was the original AHB architecture?

Answer 20

Single access:
- single address mux
- single read mux
- single write mux

Question 21

What does a multilayer AHB architecture look like?

Answer 21

One mux per main/side

Requires an arbiter for each side

Support for parallel accesses, when mains access different sides

Requires more wires

Question 22

Describe the AMBA 3.0 protocol

Answer 22

Separates the transactions: read addr, write addr, read data, write data and write response channels

OoO transaction completion

Enhanced protection support: Secure/non-secure transaction specification. Ensures that in more volatile situations critical operations are successful

Fixed mode burst support

Advanced system cache support: specify if transaction is cacheable/bufferable. Specify attributes (such as write-back/write-through)

Exclusive access (for semaphore operations)

Can do register slice support for high frequency operation

Question 23

Name a difference between AHB and AXI Burst

Answer 23

AHB:
- address and data are locked together
- have to specify address within each cycle because the side is not doing any address calculation

AXI:
- address calculation is delegated to the side
- the side automatically calculates the steps of the transfer
- the data access has to be sequential address wise
- this frees up the address port on the main
- can do simultaneous read and write transactions

Question 24

How does OoO completion differ between AHB and AXI?

Answer 24

AHB:
- if one side is slow, all data is held up
- SPLIT transactions provide very limited improvement

AXI:
- Multiple outstanding addresses, OoO completion allowed
- Fast sides may return data ahead of slow sides

Question 25

How does exclusive access work in AXI protocols

Answer 25

A main performs an exclusive read from an address location

at some later time, the main tries to complete the exclusive operation, by performing an exclusive write to the same address location

Question 26

When is an exclusive write access of the master signaled as successful?

Answer 26

No other main has written to the location betweenthe read and write accesses

Question 27

When is an exclusive write access of the master signaled as failed?

Answer 27

Another main has written to that location between the read and write accesses. In this case, the address location is not updated

Question 28

What must be included to support exclusive access?

Answer 28

The AXI side must have support for recording the address to be monitored.

When the first read happens, the side records this.