Instrucciones Aritméticas y Lógicas

Question 1

Bandera C
Bandera Z
Bandera N

Answer 1

C-Carry
Z-Zero(ult operacion=0)
N-Negative(Ult operacion neg)

Question 2

Bandera V
BANDRA S
BANDERA H

Answer 2

V-Overflow(resultados no cabe en destino)
S-Signo(signo de la ultima operacion N xor V)
H-Half Carry(generar carry de bit8 a 4)

Question 3

Bandera T

Bandera I

Answer 3

T-Almacenamiento temporal de 1 bit

I-Habiltiacion de Interrupciones

Question 4

ADD

Rd ← Rd + Rr

Answer 4

Sumar sin carry

Rd ← Rd + Rr

Question 5

LDI R17, 0X77
LDI R18,0X43
ADD R17,R18

Answer 5

R17

Question 6

ADC

Answer 6

Sumar cin carry

Rd ← Rd + Rr

Question 7

LDI R15, 0X04
LDI R16,0X10
C

Answer 7

R15

Question 8

ADIW

Rd+1:Rd ← Rd+1:Rd + K

Answer 8

d ∈ {24,26,28,30}

, 0 ≤ K ≤ 63

Question 9

LDI R27, 0X02
LDI R26,0X0E
ADIW R26,0X20

Answer 9

0X020E
0X0020
0X022E

R27

Question 10

SUB

Rd ← Rd - Rr

Answer 10

Restar sin carry

Rd ← Rd - Rr

Question 11

LDI R17, 0X77
LDI R18,0X43
SUB R17,R18

Answer 11

R17

Question 12

SUBI

Rd ← Rd - K

Answer 12

Resta registro y constante
SUBI Rd,K
16 ≤ d ≤ 31
0 ≤ K ≤ 255

Question 13

LDI R18,0X43

SUBI R18,0X77

Answer 13

R18

Question 14

Bandera Z

Answer 14

Rd=Rr Z=1

Rd≠Rr Z=0

Question 15

Bandera C

Answer 15

Rd≥Rr o k C=0

Rd

Question 16

SBC

Rd ← Rd - Rr - C

Answer 16

Restar con carry
Rd ← Rd - Rr - C
0 ≤ d ≤ 31
0 ≤ r ≤ 31

Question 17

EJEMPLO SBC

C

Answer 17

R26

Question 18

SBCI

Rd ← Rd - K - C

Answer 18

Restar constante
16 ≤ d ≤ 31
0 ≤ K ≤ 255

Question 19

EJEMPLO SBCI
LDI R28, 0X13
SBCI R28,0X2
C

Answer 19

R28

Question 20

SBIW

Answer 20

Rd+1:Rd ← Rd+1:Rd - K
d ∈ {24,26,28,30}
0 ≤ K ≤ 63

Question 21

EJEMPLO SBIW
LDI R30,2B
LDI R31,0X20
SBIW R30,0X12

Answer 21

R31

Question 22

AND

Rd ← Rd • Rr

Answer 22

Entre dos registros
1100 AND 1011
1000

Question 23

ANDI

Rd ← Rd • K

Answer 23

Registro y constante
16 ≤ d ≤ 31
0 ≤ K ≤ 255

Question 24

OR
Rd ← Rd VRr
OR R17,R18

Answer 24

R17

Question 25

ORI

Answer 25

Registro y constante
16 ≤ d ≤ 31
0 ≤ K ≤ 255

Question 26

EOR

OR exclusivo

Answer 26

EOR Rd,Rr
0 ≤ d ≤ 31
0 ≤ r ≤ 3

Question 27

COM

Answer 27

Complemento a 1

Question 28

NEG

Answer 28

Complemento a 2

Question 29

SBR
Set bit in register
Rd ← Rd v K

Answer 29

16 ≤ d ≤ 31

0 ≤ K ≤ 255

Question 30

EJEMPLO SBR

SBR R18,0XAA

Answer 30

0 1 0 0 0 0 1 1
1 0 1 0 1 0 1 0
1 1 1 0 1 0 1 1
R18

Question 31

CBR
Clear bit in register
Rd ← Rd • ($FF - K)

Answer 31

16 ≤ d ≤ 31

0 ≤ K ≤ 255

Question 32

EJEMPLO CBR

Answer 32

0 1 0 0 0 0 1 1
1 0 1 0 1 0 1 0
0 1 0 0 0 0 0 1
R18

Question 33

INC

Answer 33

Incrementar

Question 34

DEC

Answer 34

Decrementar

Question 35

TST

Rd ← Rd • Rd

Answer 35

mueve banderas z y n

Question 36

EJEMPLO TST

Answer 36

R29

Question 37

CLR

Answer 37

limpia registro
CLR R16
R16<0X00

Question 38

SER

Answer 38

set registro
SER R16
R16<0XFF

Question 39

MUL

Answer 39

R1:R0 ← Rd × Rr (unsigned ← unsigned × unsigned)

Question 40

LDI R2,0x14
LDI R28,0X13
MUL R2,R28

Answer 40

R1< -0X01

R0

Question 41

MULS

Answer 41

R1:R0 ← Rd × Rr (signed ← signed × signed)
16 ≤ d ≤ 31
16 ≤ r ≤ 31

Question 42

MULS R2,R28

Answer 42

NO VÁLIDO

Question 43

MULSU

Answer 43

R1:R0 ← Rd × Rr (signed ← signed × unsigned)
16 ≤ d ≤ 23
16 ≤ r ≤ 23

Question 44

MULSU R2,R28

Answer 44

NO VÁLIDO

Question 45

FMUL

R1:R0 ← Rd × Rr (unsigned (1.15) ← unsigned (1.7) × unsigned (1.7))

Answer 45

Multiplicacion en fraccionarios
16 ≤ d ≤ 23
16 ≤ r ≤ 23