Hardware Basics

Question 1

Karnaugh Map

Answer 1

Logic Synthesis:
-Boolean results are
transferred from a truth
table to Karnaugh map
- Allowing most often
minimal boolean
expressions
- Useful only up to 4
variables
Design Vulnerabilities
 A 3-input encoder that assigns a 2-bit code to
each of the three different inputs

Question 2

Realization of Logic Gates : CMOS Transistors

Answer 2

A CMOS gate is a system consisting of a pMOS pull-up network connected to the output 1 (or VDD) and nMOS pull-down network, connected to the output 0 (or GND).

Question 3

Design Stages of Hardware implementations

Answer 3

1. Writing HDL (RTL design)
2. Functional Verification (e.g. logic simulation)
3. Logic Synthesis (Combinational and Sequential) ⇒
   Netlist
4. Placement
5. Routing

Question 4

Hardware Description Language (HDL)

Answer 4

Schematic Designs: good for
small number of gates and
connections
- HDL can describe complicated
designs, e.g.,
-         Verilog, VHDL

Question 5

Difference between HDL and
software programming
language

Answer 5

Software language programming
is translated into machine
instruction and executed on
microprocessor
- HDL is a synthetic and semantic
for modeling
- Hardware has temporal behavior
and spatial structure

Question 6

Functional Verification

Answer 6

-Simulating the
behavior of digital
circuits and hardware
description languages
-Debugging before
synthesis of the circuit
-Giving different inputs
to the circuit and
observing the outputs

Question 7

Logic Synthesis

Answer 7

-Creating a netlist out
of gates and
connections from the
HDL code
-Optimising the design
by reducing number of
required gates

Question 8

Place and Route

Answer 8

-Placement involves
placing the
transistors, gates or
any other element on
the die
-Routing involves
wiring of electrical
elements together

Question 9

Application-specific
Integrated Circuit
(ASIC),

Answer 9

- Custom ICs for different
purposes
- Microprocessors,
Microcontrollers and GPUs
are also ASICs

Customized IC for
particular use
- System on Chip (SoC):
microprocessors + ROM
\+ RAM + EEPROM +
flash memory
- CPUs and
microcontrollers are
ASICs!

Question 10

Programmable Logic

Device (PLD), e.g.,

Answer 10

• Complex Programmable
  Logic Device (CPLD)
• Field Programmable Gate
  Array (FPGA)

Question 11

ASIC

- Gate Array Design

Answer 11

• Transistors (or Gates)
  are predefined on the
  wafer
• No interconnection (metallitzation) between
  transistors
• Based on the design,
  interconnections are defined in photolithographic process

Question 12

ASIC

- Full Custom Design

Answer 12

Everything has to be
designed and defined
for the
photolithographic
process
- Advantage: reduced
area, performance
improvement
- Disadvantage:
increased
manufacturing and
design costs

Question 13

ASIC Pros and Contras

Answer 13

Advantages:
- Designing precisely different analog characteristics
(delays, capacitance, resistance, etc)
- Optimization of gate placement and routing between
them
- Improved performance
Disadvantages:
- Static circuits (reconfiguration is not possible!)
- Expensive manufacturing

Question 14

Programmable Logic - CPLD and FPGA

Answer 14

- Reconfigurable logic device
after manufacturing
- Containing Logic Cells to
realize combinational and
sequential logic
- More complex and routing
architectures on FPGAs
- Larger numbers of logic
cells on FPGAs
- All CPLDs have internal
flash memory but most of
the FPGAs have no internal
flash memory

Question 15

Field Programmable Gate Arrays

Answer 15

-Programmable
and reconfigurable
logic devices
-Containing
programmable
logic cells to realize
combinatorial and sequential logic
functions

Question 16

Configuring an FPGA

Answer 16

Bitstream:
configuration data
for FPGAs
- Programming the
application design
once into the NVM
in a safe
environment

Question 17

FPGA Architecture

Answer 17

Multiple Configuration Logic
Blocks (CLBs) are islands
surrounded by a sea of
interconnects.
 Each CLB contains a Lookup
Table (LUT) that is
configured to implement a
primitive logic gate.
 The interconnect is also
configurable, and it connects
CLBs together so that more
complicated circuits can be
composed from the primitive
logic gates.
 The FPGA bitstream specifies
the configuration of both the
1. CLBs and the
2. interconnects

Question 18

Combinatorial Logic is realized by

Answer 18

LUTs

Question 19

Sequential Logic is realized by

Answer 19

DFFs

Question 20

LUT Architecture

Answer 20

- Putting zero and ones
to memory cells
“programs” the
desired combinational
function
-Multiple stages of
multiplexers to realize
a large LUT
Memory cells can be
SRAM, Flash or
AntiFuse cells

Question 21

FPGA Interconnect Architecture

Answer 21

-Pass transistors act
as programmable
switches
-Pass transistor gates
are driven by
configuration
memory cells

Question 22

FPGA-based Embedded System

Answer 22

 Distinct cores with varying provenance
are on the same chip. Complex tool
chains are used to generate cores.
 An AES core can be the result of
transforming HDL code to a netlist,
then to a bitstream.
 A DSP core can be the result of
transforming a DSP application to
MATLAB algorithms, then to HDL
to a netlist, then to a bitstream.
 Celoxica is a Electronic System
Level (ESL) design flow that
transforms C code to a soft
processor core.
 Finally, a C compiler such as gcc
can transform C code to an
executable, which can run on a
hard-wired processor core