General Flashcards

1
Q

True or false, decreasing response time almost always improves throughput

A

true, changing one often affects the other

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2
Q

Performance_x

A

1/execution_time_x

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3
Q

X is n times as fast as Y

A

performance_x/performance_y = execution_time_y/execution_time_x

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4
Q

CPU execution time

A

time the CPU spends computing for this task and does not wait for I/O

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5
Q

wall clock time/response time/elapsed time

A

total time to complete a task, including disk accesses, memory accesses, I/O, OS overhead, etc

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6
Q

CPU execution time

A

CPU clock cycles * clock cycle time

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7
Q

How .to improve performance

A

reducing the number of clock cycles required for a program, or the length of the lcokc cycle

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8
Q

CPU clock cycles

A

Instructions for a program * average clock cycles per instruction (CPI)

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9
Q

CPU Time in terms of instruction count

A

instruction count * CPI * clock cycle time
or
(Instruction count * CPI)/Clock rate

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10
Q

First steps of instructions:

A
  1. send program counter to the memory that contains code and fetch instructions from memory
  2. Read one or two registers, using fields of the instructions to select the registers to read
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11
Q

Three instruction classes

A

memory-reference, arithmetic-logical, branches

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12
Q

How can ALU be used?

A

memory-reference instructions use it for address calculation; arithmetic-logical for operation execution; branches for comparison

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13
Q

multiplexor

A

logic element to chose among multiple sources and steers one of those sources to its destination

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14
Q

clocking methodology

A

defines when signals can be read and when they can be written

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15
Q

edge triggered clocking

A

any values stored in a sequential logic element are updated only on a clock edge

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16
Q

control signal

A

signal used for multiplexor selection or for directing the operation of functional uint

17
Q

data signal

A

contains information that is operated on by a functional unit

18
Q

edge triggered methodology allows what?

A

a state element to be read and written in the same clock cycle w/o creating a race that leads to indeterminate data values

19
Q

register file

A

a state element that consists of a set of registers that can be read/written by specifying the register number to be accessed