final studying

Question 1

exceptions

Answer 1

events that cause the currently running program to be stopped and the operating system code to be run

Question 2

exception types

Answer 2

system calls : request to the operating system to perform some service on behalf of the application program
Internally generated : unexpected events (signed overflow for add instructions)
externally generated : interrupts , I/O device interupting processor when it has finished an operation

Question 3

how does the hardware determine what memory words to copy into cache?

Answer 3

most programs exhibit locality of reference

Question 4

spatial locality

Answer 4

words adjacent in memory to words recently accessed are likely to be accessed in the near future

Question 5

TLB

Answer 5

translation lookaside buffer : a cache for page table entries, implemented on the processor chip

Question 6

Each entry on a TLB consists of

Answer 6

a page table entry

a tag field that specifies which virtual page this entry is for

Question 7

Whats the point of a TLB

Answer 7

makes address translation fast

Question 8

First 2 steps of every instruction

Answer 8

send program counter to memory that contains the code and fetch in struction form memory
Read 1 or 2 registers, using fiels of the instruction to select registers to read. (lw only requires one register

Question 9

All instructions except _____ use the alu after________

Answer 9

jump

reading the registers

Question 10

multiplexor

Answer 10

a logic element that chooses from among multiple sources and steers one of those sources to its destination

Question 11

combinational element

Answer 11

an operational element such as an AND gate or an ALU

Question 12

state element

Answer 12

a memory element such as a register or memory

Question 13

D flip-flop

Answer 13

a state element with 2 inputs and one output

Question 14

program counter

Answer 14

a register that holds the address of the current instruction

Question 15

R-format instructions

arithmetic logical instructions

Answer 15

read two registers, perform an ALU operation on the contents of the
registers, and write the result to a register

Question 16

register file

Answer 16

a state element that consists of a set of registers that can be read and written by supplying a register number to be accessed

Question 17

The two elements needed to implement R-format ALU operations

Answer 17

register file and the ALU

Question 18

Branch datapath must do 2 operations

Answer 18

compute the branch target address

compare the register operands

Question 19

registers

Answer 19

primitives used in hardware design that are also visible to the programmer when the computer is completed

Question 20

word

Answer 20

groups of 32 bits

Question 21

reasons to not use too many registers

Answer 21

would increase cct

increase # of bits passed 32

Question 22

arithmetic operations occur

Answer 22

registers in mips instructions

Question 23

data transfer instructions

Answer 23

instructions that move data between memory to registers

Question 24

overflow

Answer 24

when the number that is the result of an operation cannot be represented by the rightmost hardware bits

when the leftmost retained bit of the of the binary bit pattern is not the same as the infinite # of digits to the left

Question 25

Two's complement is used for

Answer 25

storing binary representations for signed numbers

Question 26

sign extension

Answer 26

copy the sign repeatedly to fill the rest of the register

Question 27

register file

Answer 27

collection of registers in which any register can be read or written * stores the 32 general purpose registers of of a processor

Question 28

A law that quantifies how the system performance enhancement possible with a given improvement is limited by the amount that the improved feature is used

Answer 28

Amdahl's law

Question 29

outputs from assembly (and inputs to linking) are

Answer 29

object files

Question 30

object files

Answer 30

must contain debugging information and information for the linker to do its job * external label inforamtion * external reference information * relocation information * in addition to machine code and data

Question 31

In a 2 pass assembler

Answer 31

the assembler makes 2 complete passes through the source program * first pass: determine the memory address corresponding to each name used as a label * second pass : machine language code generated

Question 32

linking

Answer 32

combining multiple independently compiled subunits

Question 33

combinational logic circuits

Answer 33

hardware devices that implement logic functions

Question 34

normalization

Answer 34

maximize prcision when using a fixed # of digits by ensuring no leading zeros

Question 35

floating point number representation

Answer 35

only store digits and exponent

Question 36

processor parts

Answer 36

datapath, control

Question 37

datapath

Answer 37

caries out arithmetic and other operations, moves operands and results around

Question 38

process of combining multiple independently compiled subunits

Answer 38

linking

Question 39

type of digital circuit without memory, the output is a function only of the current input

Answer 39

combinational

Question 40

a memory element storing a single bit, the value of which is changed only on a clock edge

Answer 40

flip-flop

Question 41

a data structure created during the assembly process that stores for each label in a program, the memory address to which it corresponds

Answer 41

symbol table

Question 42

a program chosen to serve as the basis of performance comparison between computer systems

Answer 42

benchmark

Question 43

denorms

Answer 43

assure that when subtracting numbers very close to zero, that the answer will not be zero

Question 44

object file

Answer 44

output from the assembler/compiler * contains machine code, a list of external symbols and their values, list of external references and where they're used, and relocation information

Question 45

linker will

Answer 45

will concatenate the code segments from the object files being linked, and similarly will concatenate the data segments adds a relocaiton constant to the external label addresses before using them to fill in the external reference fields

Question 46

Risc

Answer 46

+ register-register (load-store) style + fixed-length instructions + limited addressing modes + limited operations

Question 47

Cisc

Answer 47

+ memory-memory or register-memory style + variable instruction length + many instruction formats, operations, addressing modes

Question 48

Describe what actions are carried out during each of the stages of the pipelined datapath discussed in class.

Answer 48

``` Instruction Fetch and update of PC Instruction decode and register reads Execution, using the alu, address calculation Memory access, branch completion Write Back into the register file ```

Question 49

structural hazard

Answer 49

occur when hardware can't support the combination of processing steps we want to perform in the same clock cycle

Question 50

instructions that do nothing but go inbetween instructions to prevent structural hazards

Answer 50

nop instructions

Question 51

approaches to cache coherence

Answer 51

snooping protocols: on a read miss at a processor, broadcast a message seen by other processors, if a copy of required memory block is dirty, obtain the updated memory block , single shared bus connects processors with main memory directory protocols: keep track of the caching status of each memory block, consult directory to determine where messages need to be sent

Question 52

memory-mapped i/o

Answer 52

dedicate a portion of the physical address space to registers within the I/O device interfaces registers - data buffers, status/control registers * can be accessed with using ordinary store and load instructions

Question 53

components of disk access time

Answer 53

seek time : time to move arm to track Rotational latency : time until first sector of data to be read/written rotates under the read/write head transfer time : time from when the first bit is read/written to when the last bit is read/written

Question 54

RAID1

Answer 54

2 copies of all the data, write to a mirror disk at the same time as first disk, can access either disk, expensive but dependable

Question 55

RAID5

Answer 55

An extra parity disk is added and blocks of data are added round robin, parity block is spread across disks

Question 56

hardware multithreading

Answer 56

within a single core, replicate some components so as to support execution of multiple threads

Question 57

coarse-grained multithreading

Answer 57

idea here is that when the execution of one thread suffers a major stall (e.g., owing to miss from 2nd or 3rd level cache), "quickly" switch to executing instructions from a different thread

Question 58

fine-grained multithreading

Answer 58

with this approach, switch threads every clock cycle! able to achieve higher efficiency compared to coarse-grained multithreading since don't have the pipeline "fill time" delays of the coarse-grained approach (wherein the new thread has to fill the pipeline before its instructions will start completing

Question 59

simultaneous multithreading

Answer 59

instructions from multiple different threads can be issued in the same clock cycle (with a hardware-imposed limit on the number of threads being simultaneously executed, e.g. two)

Question 60

t0-t7

Answer 60

8-15

Question 61

s0-s7

Answer 61

16-23

Question 62

t8-t9

Answer 62

24-25

Question 63

a0-a3

Answer 63

4-7

Question 64

v0-v1

Answer 64

2-3

Question 65

approaches to specifying multiple clock cycle datapath

Answer 65

finite state machines | microprograms

Question 66

pipelining

Answer 66

overlap processing of different instructions

Question 67

approaches to control hazards

Answer 67

``` delayed branches conditional instructions predicting dynamic prediction (history) ```

Question 68

dynamic branch prediction wrong if

Answer 68

branch condition different than last time | a different branch instruction executed more recently with an address that has the same low order bits

Question 69

how does the mips system know what type of exception has occured

Answer 69

puts numeric code into a special purpose register that it recognizes

Question 70

in-order commit

Answer 70

instructions not committed by writing to registers or memory

Question 71

memory hierarchy

Answer 71

processor cache memory main memory magnetic disk

Question 72

nonvolative

Answer 72

data is retained when device is powered down

Question 73

processor cache is managed by

Answer 73

hardware

Question 74

hit latency

Answer 74

the time it takes to look in the cache and retrieve the requested data

Question 75

miss rate

Answer 75

fraction of memory references not found in the cache

Question 76

miss penalty

Answer 76

in the case of a cache miss the time required for a block to be retrieved from the next level of cache memory