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CMPT 215 > final studying > Flashcards

final studying Flashcards

1
Q

exceptions

A

events that cause the currently running program to be stopped and the operating system code to be run

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2
Q

exception types

A

system calls : request to the operating system to perform some service on behalf of the application program
Internally generated : unexpected events (signed overflow for add instructions)
externally generated : interrupts , I/O device interupting processor when it has finished an operation

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3
Q

how does the hardware determine what memory words to copy into cache?

A

most programs exhibit locality of reference

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4
Q

spatial locality

A

words adjacent in memory to words recently accessed are likely to be accessed in the near future

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5
Q

TLB

A

translation lookaside buffer : a cache for page table entries, implemented on the processor chip

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6
Q

Each entry on a TLB consists of

A

a page table entry

a tag field that specifies which virtual page this entry is for

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7
Q

Whats the point of a TLB

A

makes address translation fast

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8
Q

First 2 steps of every instruction

A

send program counter to memory that contains the code and fetch in struction form memory
Read 1 or 2 registers, using fiels of the instruction to select registers to read. (lw only requires one register

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9
Q

All instructions except _____ use the alu after________

A

jump

reading the registers

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10
Q

multiplexor

A

a logic element that chooses from among multiple sources and steers one of those sources to its destination

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11
Q

combinational element

A

an operational element such as an AND gate or an ALU

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12
Q

state element

A

a memory element such as a register or memory

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13
Q

D flip-flop

A

a state element with 2 inputs and one output

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14
Q

program counter

A

a register that holds the address of the current instruction

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15
Q

R-format instructions

arithmetic logical instructions

A

read two registers, perform an ALU operation on the contents of the
registers, and write the result to a register

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16
Q

register file

A

a state element that consists of a set of registers that can be read and written by supplying a register number to be accessed

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17
Q

The two elements needed to implement R-format ALU operations

A

register file and the ALU

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18
Q

Branch datapath must do 2 operations

A

compute the branch target address

compare the register operands

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19
Q

registers

A

primitives used in hardware design that are also visible to the programmer when the computer is completed

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20
Q

word

A

groups of 32 bits

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21
Q

reasons to not use too many registers

A

would increase cct

increase # of bits passed 32

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22
Q

arithmetic operations occur

A

registers in mips instructions

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23
Q

data transfer instructions

A

instructions that move data between memory to registers

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24
Q

overflow

A

when the number that is the result of an operation cannot be represented by the rightmost hardware bits

when the leftmost retained bit of the of the binary bit pattern is not the same as the infinite # of digits to the left

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25
Q

Two’s complement is used for

A

storing binary representations for signed numbers

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26
Q

sign extension

A

copy the sign repeatedly to fill the rest of the register

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27
Q

register file

A

collection of registers in which any register can be read or written
* stores the 32 general purpose registers of of a processor

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28
Q

A law that quantifies how the system performance enhancement possible with a given improvement is limited by the amount that the improved feature is used

A

Amdahl’s law

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29
Q

outputs from assembly (and inputs to linking) are

A

object files

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30
Q

object files

A

must contain debugging information and information for the linker to do its job

  • external label inforamtion
  • external reference information
  • relocation information
  • in addition to machine code and data
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31
Q

In a 2 pass assembler

A

the assembler makes 2 complete passes through the source program

  • first pass: determine the memory address corresponding to each name used as a label
  • second pass : machine language code generated
32
Q

linking

A

combining multiple independently compiled subunits

33
Q

combinational logic circuits

A

hardware devices that implement logic functions

34
Q

normalization

A

maximize prcision when using a fixed # of digits by ensuring no leading zeros

35
Q

floating point number representation

A

only store digits and exponent

36
Q

processor parts

A

datapath, control

37
Q

datapath

A

caries out arithmetic and other operations, moves operands and results around

38
Q

process of combining multiple independently compiled subunits

A

linking

39
Q

type of digital circuit without memory, the output is a function only of the current input

A

combinational

40
Q

a memory element storing a single bit, the value of which is changed only on a clock edge

A

flip-flop

41
Q

a data structure created during the assembly process that stores for each label in a program, the memory address to which it corresponds

A

symbol table

42
Q

a program chosen to serve as the basis of performance comparison between computer systems

A

benchmark

43
Q

denorms

A

assure that when subtracting numbers very close to zero, that the answer will not be zero

44
Q

object file

A

output from the assembler/compiler
* contains machine code, a list of external symbols and their values, list of external references and where they’re used, and relocation information

45
Q

linker will

A

will concatenate the code segments from the object files being linked, and similarly will concatenate the data segments

adds a relocaiton constant to the external label addresses before using them to fill in the external reference fields

46
Q

Risc

A

+ register-register (load-store) style
+ fixed-length instructions
+ limited addressing modes
+ limited operations

47
Q

Cisc

A

+ memory-memory or register-memory style
+ variable instruction length
+ many instruction formats, operations, addressing modes

48
Q

Describe what actions are carried out during each of the stages of the pipelined datapath discussed in class.

A 
Instruction Fetch and update of PC
Instruction decode and register reads
Execution, using the alu, address calculation
Memory access, branch completion
Write Back into the register file
49
Q

structural hazard

A

occur when hardware can’t support the combination of processing steps we want to perform in the same clock cycle

50
Q

instructions that do nothing but go inbetween instructions to prevent structural hazards

A

nop instructions

51
Q

approaches to cache coherence

A

snooping protocols: on a read miss at a processor, broadcast a message seen by other processors, if a copy of required memory block is dirty, obtain the updated memory block , single shared bus connects processors with main memory
directory protocols: keep track of the caching status of each memory block, consult directory to determine where messages need to be sent

52
Q

memory-mapped i/o

A

dedicate a portion of the physical address space to registers within the I/O device interfaces
registers - data buffers, status/control registers
* can be accessed with using ordinary store and load instructions

53
Q

components of disk access time

A

seek time : time to move arm to track
Rotational latency : time until first sector of data to be read/written rotates under the read/write head
transfer time : time from when the first bit is read/written to when the last bit is read/written

54
Q

RAID1

A

2 copies of all the data, write to a mirror disk at the same time as first disk, can access either disk, expensive but dependable

55
Q

RAID5

A

An extra parity disk is added and blocks of data are added round robin, parity block is spread across disks

56
Q

hardware multithreading

A

within a single core, replicate some components so as to support execution of multiple threads

57
Q

coarse-grained multithreading

A

idea here is that when the execution of one thread suffers a major stall (e.g., owing to miss from 2nd or 3rd level cache), “quickly” switch to executing instructions from a different thread

58
Q

fine-grained multithreading

A

with this approach, switch threads every clock cycle! able to achieve higher efficiency compared to coarse-grained multithreading since don’t have the pipeline “fill time” delays of the coarse-grained approach (wherein the new thread has to fill the pipeline before its instructions will start completing

59
Q

simultaneous multithreading

A

instructions from multiple different threads can be issued in the same clock cycle (with a hardware-imposed limit on the number of threads being simultaneously executed, e.g. two)

60
Q

t0-t7

A

8-15

61
Q

s0-s7

A

16-23

62
Q

t8-t9

A

24-25

63
Q

a0-a3

A

4-7

64
Q

v0-v1

A

2-3

65
Q

approaches to specifying multiple clock cycle datapath

A

finite state machines

microprograms

66
Q

pipelining

A

overlap processing of different instructions

67
Q

approaches to control hazards

A 
delayed branches
conditional instructions
predicting
dynamic prediction (history)
68
Q

dynamic branch prediction wrong if

A

branch condition different than last time

a different branch instruction executed more recently with an address that has the same low order bits

69
Q

how does the mips system know what type of exception has occured

A

puts numeric code into a special purpose register that it recognizes

70
Q

in-order commit

A

instructions not committed by writing to registers or memory

71
Q

memory hierarchy

A

processor cache memory
main memory
magnetic disk

72
Q

nonvolative

A

data is retained when device is powered down

73
Q

processor cache is managed by

A

hardware

74
Q

hit latency

A

the time it takes to look in the cache and retrieve the requested data

75
Q

miss rate

A

fraction of memory references not found in the cache

76
Q

miss penalty

A

in the case of a cache miss the time required for a block to be retrieved from the next level of cache memory

CMPT 215 (8 decks)

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