Final Flashcards
study of final
R Type datapath
- PC counter increments by 4
- instruction goes to read register 1 & 2, read data 1 & 2 is fed into ALU
- instruction goes to write register, ALU result goes to write data without going through data memory
Load datapath
- PC counter increments by 4
- instruction foes to read register 1 and sign extender, read data 1 and sign extender output goes to ALU, ALU result foes to address of data memory
- instruction goes to write register, read data from data memory goes to write data
Store datapath
- PC counter increments by 4
- Instruction goes to read register 1, [4 0] read register 2, and sign extender, read data 1 and sign extender output goes to ALU
- ALU result goes to address and read data 2 goes to write data in data memory
Brach datapath
- PC counter becomes the alu result of the top right ALU
- instruction goes to register 2 [4 0] and read data 2 goes to ALU
- PC counter goes to top right ALU, instruction goes to sign extender, sign extender output goes to shift left 2 which is fed into top right ALU, ALU zero is fed into AND gate which sets MUX to 1
LDUR instruction control bits
ALUOp: 00
Instruction operation: load register
Opcode field: xxxxxxxxxxx
Desired ALU action: add
ALU control input: 0010
STUR instruction control bits
ALUOp: 00
Instruction operation: store register
Opcode field: xxxxxxxxxxx
Desired ALU action: add
ALU control input: 0010
CBZ instruction control bits
ALUOp: 01
Instruction operation: compare and branch on zero
Opcode field: xxxxxxxxxxx
Desired ALU action: pass input b
ALU control input: 0111
R-Type instuction control bits ADD
ALUOp: 10
Instruction operation: ADD
Opcode field: 10001011000
Desired ALU action: add
ALU control input: 0010
R-Type instuction control bits SUB
ALUOp: 10
Instruction operation: SUB
Opcode field: 11001011000
Desired ALU action: subtract
ALU control input: 0110
R-Type instuction control bits AND
ALUOp: 10
Instruction operation: AND
Opcode field: 10001010000
Desired ALU action: and
ALU control input: 0000
R-Type instuction control bits ORR
ALUOp: 10
Instruction operation: ORR
Opcode field: 10101010000
Desired ALU action: or
ALU control input: 0001
ideal pipelined clock cycle =
unpipelined clock cycle / # of stages
actual pipelined clock cycle is limited to being as low as the longest individual operation
instruction fetch
the instruction is read from memory using the address in the PC and then is placed in the IF/ID pipeline register. Stage occurs before instruction is identified
instruction decode and register read
instruction in the IF/ID pipeline register supplies the register numbers for reading two registers and extends the sign of the 16-bit immediate. These three 32-bit values are all stored in the ID/EX pipelining register
execute and effective address calculation
the effective address is placed in the EX/MEM pipeline register
memory
the data is written to memory
Write back
data is written back to write data in ID
full pipeline progression
IM (instruction memory/fetch)
Reg (instruction decode and register read)
ALU (execute and effective address calculation)
DM (data memory)
Reg (write back)
data hazard
when an instruction calls for a register in a clock cycle before it has been assigned its value from the previous instruction
forwarding
when a data hazard can be avoided by “pushing forward” the value of a register from a step before its actually assigned but after its calculated
stalling/bubbling
when you have to stall before an instruction is run by running “no op” instructions that push back the assigning of a register until it is given its value by the previous instruction. Should be avoided when possible
