Final Flashcards
Central Limit Theorem
if you have a large enough sample size of independent and identically distributed random variables, their sample mean will be approximately normally distributed, regardless of the shape of the original distribution.
Probability Density Function (PDF):
a function that defines the probability that a randomly chosen sample X from population/sample fall near a particular value
is the highest voltage at the input of a logic device that the device will recognize as a logic low, or Boolean false
Vil
is the lowest voltage at the input of a logic device that the device will recognize as a logic high, or Boolean true
Vih
is the maximum voltage at the output of a logic device when it is in a logic low state, subject to sourcing the specified current Iol
Vol
is the minimum voltage at the output of a logic device when it is in a logic high state, subject to sinking the specified current Ioh
Voh
is the maximum current at the output of a logic device that it can sink and still maintain an acceptable logic low voltage
I_ol
is the maximum current at the output of a logic device that it can source and still maintain an acceptable logic high voltage
Ioh
is the maximum current a logic device will source at its input when presented with a logic low input
Iil
is the maximum current a logic device will sink at its input when presented with a logic high input
Iih
Is the study of how engineers choose to optimize their designs and construction methods to produce objects and systems that will optimize their efficiency and hence the satisfaction of their clients.
Engineering economics
Elements of a Test Plan
- Continuity
- Functionality
- Power Consumption
- Leakage Current
Best Practice for Creating a Test Plan
- Determine what information needs to be found that is not the datasheet.
- Explanation of each test and the relation to the datasheet
- List and explain test condition.
- Hardware Setup Diagram
Why make a test plan?
- To allow design engineers and test engineers to agree upon a set of tests that will guarantee the quality of a product once it is produced.
Three properties that define a single stuck-at fault:
Only one line is faulty.
The faulty line is permanently set to 0 or 1
The fault can be at an input or output of a gate
Checkpoint theorem
A test set that detects all single (multiple) stuck-at faults on all checkpoints of a combinational circuit, also detects all single (multiple) stuck-at faults in that circuit.
Why Model Faults?
o I/O functions tests are inadequate for manufacturing.
o Real defects (often mechanical) are too numerous and often not analyzable.
o A fault model identifies targets for testing and makes analysis possible.
What’s an infant mortal?
o Infant mortality: includes products that are misprocessed and fail very early, much less than design lifetime.
What does failure rate look like over lifetime?
see failure rate vs lifetime graph
Value and risks of concurrent engineering
o Concurrent engineering eliminates a lot of that wait time by overlapping and integrating tasks.
o It relies on everyone working together; hence communication is critical. Room for mistakes is small as it impacts all the departments or disciplines involved
What does profit over time look like?
o Time to Market plot
What are the nonlinear effects of being first to market?
Reduced Cost: Optimal product developed requires less resources.
Time to market:
- Reduced Cost: Optimal product developed requires less resources.
- Foster ROI: New products generate profit sooner.
- Increased Value:
Concurrent engineering/configuration management:
Concurrent engineering eliminates a lot of that wait time by overlapping and integrating tasks by breaking tasks into groups:
Burn-in/accelerated testing
Subject chips to high temperature and over voltage supply, while running production tests.
What does burn-in test catch?
Infant mortality cases: Damaged chips that fail early in the operation.
Freak Failures: Devices having some failure mechanisms as reliable devices.
Validation/Characterization test
- Verifies correctness of design and of test procedure – usually requires correction to design.
- Worst case test: Choose test that passes/fails chips.
Verification vs. Test:
- Verification – verifies the correctness of design. Performed by simulation, hardware emulation, or formal methods.
- Test – Verifies correctness of manufactured hardware.
o Two Part Process of test?
Test Generation: Software process executed during design.
Test Application: Electrical Test applied to hardware.
Roles of testing
- Detection: Determination whether the device under test (DUT) has some fault.
- Diagnosis: Identification of a specific fault that is present on DUT.
- Device characterization: Determination and correction of errors in design and/or test procedure.
- Failure mode analysis (FMA): Determination of manufacturing process errors that may have caused defects on the DUT.
End of Life Mechanism for CMOS Electronic:
- Time Dependent Dielectric Breakdown (TDDB): Due to increasing charges trapped in the oxide.
- Channel Hot Electron effects: Causes traps at the oxide silicon interface and shifts transistor threshold voltages.
- Electromigration: In which current results in the transport of material in conductive lines and eventual failures in these lines (opens and shorts)
Features of the Failure Rate vs. Lifetime Curve:
- Infant mortality: includes products that are misprocessed and fail very early, much less than design lifetime.
- Random fails: occur over the life of the product and hopefully a very small percentage.
- Wear out: is where end of life mechanisms begins to show up in a large percentage of products.
what is Design for test
refers to hardware design styles or added hardware that reduces test generation complexity. Considering the life-cycle cost; Design for test on chip may impact the costs at board and system levels.
Design for test – cost/benefit
- Cost – reduced yield due to area overhead, yield loss due to non-functional tests
- Benefits – Reduced ATE cost due to self-test, inexpensive alternatives to burn-in test
CMOS Dominant technology, inherently low power – why?
Because it has very low power since it draws no current.
CMOS is inherently more complicated to produce – why?
More complicated to produce because of the opposite polarity silicon.
Minimizing error: what are the three?
- Averaging
- Guardbanding
- Filtering
Minimizing error: Averaging
Form of discrete-time filtering. By averaging more samples, the answer becomes more repeatable and reliable. Must balance need for more repeatability with time taken to take extra measurements.
Minimizing error: Guardbanding
If measurement known to be accurate and repeatable with worst-case uncertainty of ±ε, we tighten the final test limits from the data sheet specification limits by ε. Unfortunately rejects good devices. Reduce ε by improving repeatability at the cost of longer test times.
Minimizing error: Filtering
Analog filters are used to remove unwanted signal components before measurement. Low-pass filters with a low cutoff frequency are often used. Reduces noise and increases repeatability but increases test time.
Types of error
- Systematic Error: Show up consistently from measurement to measurement; reduced through calibration processes.
- Random Error: Non-repeatable errors are usually caused by thermal noise or other noise sources in either the DUT or the tester hardware.
- Resolution and Quantization Error: limited resolution due to conversion of continuous analog signals to discrete digital signals
- Repeatability:
Relates to the distribution of values measured by the same instrument, operator, and environmental factors. It is a measure of the noise in a single gauge.
- Reproducibility
Relates to the distribution of values measured by a number of different instruments, operated by different technicians, at different sites, and under varying environmental conditions. It is a measure of the uncertainty involved in an entire site of measurement/test instruments and team of test engineers/technicians.
We want the Measurement Cp to be _____
50 or higher
Yield loss
refers to the reduction in the number of acceptable or conforming units due to defects.
Defect level
refers to the number or proportion of defective units or components in a production or measurement process
What is fault coverage?
percentage of detected faults in a total population
Real measurements can fail due to various factors, such:
- Instrumental errors
- Human errors
- Environmental factors
Instrumental errors
miscalibrations drifts measurement limitations
Human errors
improper technique, misinterpretation
Environmental factors
temperature, humidity, or electromagnetic interference
Accuracy:
Overall closeness of a measurement to the true value
Precision
Obtaining the same measurement when repeated
What is Process capability index, Cpk
Measures the process capability with respect to centering between specification limits
What value should process capability be to achieve 6σ?
Must be >= 1.5 to achieve 6σ
Process potential index, Cp:
Is the ratio between the range of passing values and the process capability
Process capability:
A measure of the ability of a process to produce output that meets the customer’s specifications
Sigma must be ___ of the range between the USL and LSL.
1/12
Six sigma quality aims for a defect rate of ___ ppm
3.4 parts per million (ppm)
o The mean of the distribution of values must be no more than ___ sigma from the target value, generally the midpoint of USL, LSL.
1.5
The generally accepted measurements of compliance are Cp > __ and Cpk > __
2, 1.5
Shmoo Plot:
graphical representation of test results that shows how a device or component performs under different test conditions
Wafer Map
displays the location and status of individual devices or components on the wafer
Mean:
represents the most probable value of a measured variable. It corresponds to the average value of the population.
Standard Deviation
measures the amount of variation or dispersion in a set of values. It provides a way to understand how spread out or close together the data points are from the mean
What are the elements of statistical process control?
- Identification of critical process elements and their indicators
- establish a culture of continuous improvement in which we look at excursions from the control limits established for the process variables we have established
- method of investigating and identifying root causes of the excursions
The range from μ - σ to μ
34.1% of the data
The range from μ - 2σ to μ
47.7% of the data
The range from μ - 3σ to μ
49.9% of the data
±1σ = __
68%
±2σ = __
95%
±3σ = __
99.7%
