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Parametrics > Final > Flashcards

Final Flashcards

1
Q

Central Limit Theorem

A

if you have a large enough sample size of independent and identically distributed random variables, their sample mean will be approximately normally distributed, regardless of the shape of the original distribution.

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2
Q

Probability Density Function (PDF):

A

a function that defines the probability that a randomly chosen sample X from population/sample fall near a particular value

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3
Q

is the highest voltage at the input of a logic device that the device will recognize as a logic low, or Boolean false

A

Vil

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4
Q

is the lowest voltage at the input of a logic device that the device will recognize as a logic high, or Boolean true

A

Vih

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5
Q

is the maximum voltage at the output of a logic device when it is in a logic low state, subject to sourcing the specified current Iol

A

Vol

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6
Q

is the minimum voltage at the output of a logic device when it is in a logic high state, subject to sinking the specified current Ioh

A

Voh

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7
Q

is the maximum current at the output of a logic device that it can sink and still maintain an acceptable logic low voltage

A

I_ol

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8
Q

is the maximum current at the output of a logic device that it can source and still maintain an acceptable logic high voltage

A

Ioh

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9
Q

is the maximum current a logic device will source at its input when presented with a logic low input

A

Iil

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10
Q

is the maximum current a logic device will sink at its input when presented with a logic high input

A

Iih

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11
Q

Is the study of how engineers choose to optimize their designs and construction methods to produce objects and systems that will optimize their efficiency and hence the satisfaction of their clients.

A

Engineering economics

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12
Q

Elements of a Test Plan

A
  • Continuity
  • Functionality
  • Power Consumption
  • Leakage Current
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13
Q

Best Practice for Creating a Test Plan

A
  • Determine what information needs to be found that is not the datasheet.
  • Explanation of each test and the relation to the datasheet
  • List and explain test condition.
  • Hardware Setup Diagram
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14
Q

Why make a test plan?

A
  • To allow design engineers and test engineers to agree upon a set of tests that will guarantee the quality of a product once it is produced.
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15
Q

Three properties that define a single stuck-at fault:

A

Only one line is faulty.
The faulty line is permanently set to 0 or 1
The fault can be at an input or output of a gate

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16
Q

Checkpoint theorem

A

A test set that detects all single (multiple) stuck-at faults on all checkpoints of a combinational circuit, also detects all single (multiple) stuck-at faults in that circuit.

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17
Q

Why Model Faults?

A

o I/O functions tests are inadequate for manufacturing.
o Real defects (often mechanical) are too numerous and often not analyzable.
o A fault model identifies targets for testing and makes analysis possible.

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18
Q

What’s an infant mortal?

A

o Infant mortality: includes products that are misprocessed and fail very early, much less than design lifetime.

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19
Q

What does failure rate look like over lifetime?

A

see failure rate vs lifetime graph

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20
Q

Value and risks of concurrent engineering

A

o Concurrent engineering eliminates a lot of that wait time by overlapping and integrating tasks.
o It relies on everyone working together; hence communication is critical. Room for mistakes is small as it impacts all the departments or disciplines involved

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21
Q

What does profit over time look like?

A

o Time to Market plot

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22
Q

What are the nonlinear effects of being first to market?

A

Reduced Cost: Optimal product developed requires less resources.

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23
Q

Time to market:

A
  1. Reduced Cost: Optimal product developed requires less resources.
  2. Foster ROI: New products generate profit sooner.
  3. Increased Value:
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24
Q

Concurrent engineering/configuration management:

A

Concurrent engineering eliminates a lot of that wait time by overlapping and integrating tasks by breaking tasks into groups:

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25
Q

Burn-in/accelerated testing

A

Subject chips to high temperature and over voltage supply, while running production tests.

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26
Q

What does burn-in test catch?

A

Infant mortality cases: Damaged chips that fail early in the operation.
Freak Failures: Devices having some failure mechanisms as reliable devices.

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27
Q

Validation/Characterization test

A
  • Verifies correctness of design and of test procedure – usually requires correction to design.
  • Worst case test: Choose test that passes/fails chips.
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28
Q

Verification vs. Test:

A
  • Verification – verifies the correctness of design. Performed by simulation, hardware emulation, or formal methods.
  • Test – Verifies correctness of manufactured hardware.
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29
Q

o Two Part Process of test?

A

Test Generation: Software process executed during design.
Test Application: Electrical Test applied to hardware.

30
Q

Roles of testing

A
  • Detection: Determination whether the device under test (DUT) has some fault.
  • Diagnosis: Identification of a specific fault that is present on DUT.
  • Device characterization: Determination and correction of errors in design and/or test procedure.
  • Failure mode analysis (FMA): Determination of manufacturing process errors that may have caused defects on the DUT.
31
Q

End of Life Mechanism for CMOS Electronic:

A
  • Time Dependent Dielectric Breakdown (TDDB): Due to increasing charges trapped in the oxide.
  • Channel Hot Electron effects: Causes traps at the oxide silicon interface and shifts transistor threshold voltages.
  • Electromigration: In which current results in the transport of material in conductive lines and eventual failures in these lines (opens and shorts)
32
Q

Features of the Failure Rate vs. Lifetime Curve:

A
  • Infant mortality: includes products that are misprocessed and fail very early, much less than design lifetime.
  • Random fails: occur over the life of the product and hopefully a very small percentage.
  • Wear out: is where end of life mechanisms begins to show up in a large percentage of products.
33
Q

what is Design for test

A

refers to hardware design styles or added hardware that reduces test generation complexity. Considering the life-cycle cost; Design for test on chip may impact the costs at board and system levels.

34
Q

Design for test – cost/benefit

A
  • Cost – reduced yield due to area overhead, yield loss due to non-functional tests
  • Benefits – Reduced ATE cost due to self-test, inexpensive alternatives to burn-in test
35
Q

CMOS Dominant technology, inherently low power – why?

A

Because it has very low power since it draws no current.

36
Q

CMOS is inherently more complicated to produce – why?

A

More complicated to produce because of the opposite polarity silicon.

37
Q

Minimizing error: what are the three?

A
  • Averaging
  • Guardbanding
  • Filtering
38
Q

Minimizing error: Averaging

A

Form of discrete-time filtering. By averaging more samples, the answer becomes more repeatable and reliable. Must balance need for more repeatability with time taken to take extra measurements.

39
Q

Minimizing error: Guardbanding

A

If measurement known to be accurate and repeatable with worst-case uncertainty of ±ε, we tighten the final test limits from the data sheet specification limits by ε. Unfortunately rejects good devices. Reduce ε by improving repeatability at the cost of longer test times.

40
Q

Minimizing error: Filtering

A

Analog filters are used to remove unwanted signal components before measurement. Low-pass filters with a low cutoff frequency are often used. Reduces noise and increases repeatability but increases test time.

41
Q

Types of error

A
  • Systematic Error: Show up consistently from measurement to measurement; reduced through calibration processes.
  • Random Error: Non-repeatable errors are usually caused by thermal noise or other noise sources in either the DUT or the tester hardware.
  • Resolution and Quantization Error: limited resolution due to conversion of continuous analog signals to discrete digital signals
42
Q
  • Repeatability:
A

Relates to the distribution of values measured by the same instrument, operator, and environmental factors. It is a measure of the noise in a single gauge.

43
Q
  • Reproducibility
A

Relates to the distribution of values measured by a number of different instruments, operated by different technicians, at different sites, and under varying environmental conditions. It is a measure of the uncertainty involved in an entire site of measurement/test instruments and team of test engineers/technicians.

44
Q

We want the Measurement Cp to be _____

A

50 or higher

45
Q

Yield loss

A

refers to the reduction in the number of acceptable or conforming units due to defects.

46
Q

Defect level

A

refers to the number or proportion of defective units or components in a production or measurement process

47
Q

What is fault coverage?

A

percentage of detected faults in a total population

48
Q

Real measurements can fail due to various factors, such:

A
  • Instrumental errors
  • Human errors
  • Environmental factors
49
Q

Instrumental errors

A

miscalibrations drifts measurement limitations

50
Q

Human errors

A

improper technique, misinterpretation

51
Q

Environmental factors

A

temperature, humidity, or electromagnetic interference

52
Q

Accuracy:

A

Overall closeness of a measurement to the true value

53
Q

Precision

A

Obtaining the same measurement when repeated

54
Q

What is Process capability index, Cpk

A

Measures the process capability with respect to centering between specification limits

55
Q

What value should process capability be to achieve 6σ?

A

Must be >= 1.5 to achieve 6σ

56
Q

Process potential index, Cp:

A

Is the ratio between the range of passing values and the process capability

57
Q

Process capability:

A

A measure of the ability of a process to produce output that meets the customer’s specifications

58
Q

Sigma must be ___ of the range between the USL and LSL.

A

1/12

59
Q

Six sigma quality aims for a defect rate of ___ ppm

A

3.4 parts per million (ppm)

60
Q

o The mean of the distribution of values must be no more than ___ sigma from the target value, generally the midpoint of USL, LSL.

A

1.5

61
Q

The generally accepted measurements of compliance are Cp > __ and Cpk > __

A

2, 1.5

62
Q

Shmoo Plot:

A

graphical representation of test results that shows how a device or component performs under different test conditions

63
Q

Wafer Map

A

displays the location and status of individual devices or components on the wafer

64
Q

Mean:

A

represents the most probable value of a measured variable. It corresponds to the average value of the population.

65
Q

Standard Deviation

A

measures the amount of variation or dispersion in a set of values. It provides a way to understand how spread out or close together the data points are from the mean

66
Q

What are the elements of statistical process control?

A
  • Identification of critical process elements and their indicators
  • establish a culture of continuous improvement in which we look at excursions from the control limits established for the process variables we have established
  • method of investigating and identifying root causes of the excursions
67
Q

The range from μ - σ to μ

A

34.1% of the data

68
Q

The range from μ - 2σ to μ

A

47.7% of the data

69
Q

The range from μ - 3σ to μ

A

49.9% of the data

70
Q

±1σ = __

A

68%

71
Q

±2σ = __

A

95%

72
Q

±3σ = __

A

99.7%

Parametrics (1 decks)

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