Fetch Execute Cycle Flashcards

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1
Q

General purpose

register

A

a register not assigned a specific role by the processor designer. Programmers may use general-purpose registers.

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2
Q

Dedicated

register

A

a register assigned a specific role by the processor designer. Programmers may use some but not all dedicated registers

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3
Q

Program Counter

A

Stores the address of the next instruction to be executed

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4
Q

Memory Address Register

A

Stores the data or instruction being transferred to and from the immediate access store

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5
Q

Current Instruction Register

A

Register that is part of a CPU’s control unit and stores

the instruction currently being executed or decoded.

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6
Q

Accumulator

A

Stores results of arithmetic and logic operations

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7
Q

Bus

A

Set of parallel wires connecting independent components of a computer system

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8
Q

Address bus

A

Carries an identification (i.e. physical address) about where the data are being sent (uni-directional)

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9
Q

Data bus

A

Carries the actual data or instruction to be processed between the CPU and the other internal components such as main memory and I/O ports (bidirectional)

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10
Q

Control bus

A

Carries commands from the control unit and returns status signals from the devices such as timing signals,
acknowledgement signals and read/write signals (bidirectional)

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11
Q

ALU

A

Arithmetic Logic Unit. A digital circuit (component) used to process and manipulate data / performs calculations / logical operations.

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12
Q

Control Unit

A

It is a component of a CPU. Control unit directs the operations of the processor. It tells the computer’s memory, arithmetic/logic unit and input and output devices how to respond to a program’s instructions.

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13
Q

Decoder

A

The decoder is the circuit inside the control unit that decodes an op-code from the CIR.

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14
Q

Memory Data/Buffer Register

A

A two-way register that holds data fetched from memory ( and ready for the CPU to process) or data waiting to be stored in memory)

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15
Q

Fetch execute cycle

A

PC -next address

MAR

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